Aditya Upadhyay

Software Engineer

Bengaluru, Karnataka, India13 yrs 11 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in Physical Design and Machine Learning.
  • Proven track record in SOC optimization and performance enhancement.
  • Strong educational background from IIT Kanpur.
Stackforce AI infers this person is a Semiconductor Engineering Specialist with expertise in Physical Design and Machine Learning.

Contact

Skills

Core Skills

Physical DesignMachine LearningDevice Engineering

Other Skills

Area OptimizationAutomationCC++Computer ArchitectureCongestion OptimizationConvex OptimizationData AnalysisDevice Design OptimizationDigital Circuit DesignFloor PlanningJavaLow-power DesignMachine Learning techniquesMatlab

About

Experienced Senior Engineer with a demonstrated history of working in the computing industry. Skilled in Physical Design, Machine Learning . Strong engineering professional graduated from Indian Institute of Technology, Kanpur.

Experience

Google

Hardware Engineer

Dec 2020Present · 5 yrs 3 mos · India

  • RTL2GDS implementation for Cache Coherent Interconnect IP , Congestion and Power Optimization, Automation of Functional/Timing Eco, Leading through Mentoring
RTL2GDS implementationCongestion OptimizationPower OptimizationAutomationPhysical DesignMachine Learning

Qualcomm

Senior Engineer

May 2018Dec 2020 · 2 yrs 7 mos · Bengaluru Area, India

  • Works on SOC Power ,Performance and Area Optimizations, develops Machine Learning techniques on SOC data.
  • Works on Floor Planning , Place and Rout and Static Timing analysis
  • Familiar with Cadence First Encounter , Synopsys Prime Time ,PT PX
SOC Power OptimizationPerformance OptimizationArea OptimizationMachine Learning techniquesFloor PlanningPlace and Route+3

Intel corporation

Design Engineer

Jun 2015May 2018 · 2 yrs 11 mos · Bengaluru Area, India

  • Physical Design and execution Register Files blocks for Intel CPU core.
  • Power Performance and area optimization
Physical DesignPower OptimizationPerformance OptimizationArea Optimization

Indian institute of technology, kanpur

Graduate Student

May 2013May 2015 · 2 yrs

Fairchild - now part of on semiconductor

Device Engineer

Jun 2011Jul 2012 · 1 yr 1 mo · Pune Area, India

  • Device Design Optimization for Gallium Nitride based HEMT device
  • Performance modelling for High Voltage and High Frequency semiconductor devices
Device Design OptimizationPerformance ModellingDevice Engineering

Education

Indian Institute of Technology, Kanpur

Jan 2013Jan 2015

Indian Institute of Technology, Kanpur

Bachelor of Technology - BTech — Electrical and Electronics Engineering

Jan 2007Jan 2011

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