Amsaveni Chandran — Software Engineer
Senior Verification Engineer with almost 6 years of experience. Development of module level and top-level verification plan document. Hands on experience in IP verification using System Verilog & UVM Hands on experience in Developing Test Bench environment. Explicit experience in functional coverage and Assertions. Involved in RAL model creation. Hands on experience in creating APB BFM Hands on experience in VIP Integration Creating Verification document
Stackforce AI infers this person is a Semiconductor Verification Engineer with extensive experience in IP verification and test bench development.
Location: Erode, Tamil Nadu, India
Experience: 7 yrs 8 mos
Skills
- Design Verification Testing
- Functional Verification
Career Highlights
- Almost 6 years of experience in verification engineering.
- Expertise in System Verilog and UVM for IP verification.
- Proficient in developing comprehensive verification plans.
Work Experience
MediaTek
Staff Engineer (1 yr 5 mos)
Tech Mahindra Cerium Pvt Ltd
Senior Verification Engineer (4 yrs 8 mos)
Tech Mahindra Cerium
Senior Design Verification Engineer (4 yrs 8 mos)
HCL Technologies
Member Of Technical Staff (3 yrs)
Design Verification Engineer (2 yrs 3 mos)
Education
Bachelor of Engineering at Government College of Technology, Coimbatore
Diploma of Education at Government Polytechnic College Coimbatore
