Mar 2017 – Aug 2022 · 5 yrs 5 mos · Bangalore

Apr 2016 – Mar 2017 · 11 mos · Bangalore

Sep 2013 – Apr 2016 · 2 yrs 7 mos · Bangalore

Dec 2004 – Aug 2013 · 8 yrs 8 mos

• Analog lead: Analog and Power Management architecture definition for Connectivity multiradio SOCs with integrated DC-DCs, capless LDOs, clock management, low power pll and SERDES. Mentored teams for power and clock management circuit design. Responsible for SOC floorplan, analog connectivity, full chip ESD, thermal analysis and coex performance improvements of multiradio SOCs.

Jun 2000 – Dec 2004 · 4 yrs 6 mos

• Analog Circuit designer for standard analog and power management products: Designed and characterized power management circuit blocks (boost DC-DC, bandgap reference, UVLO, POR, Oscillator) in PMIC products. Top level and block level simulation of PMIC chips involving DC-DC converters, LDO, battery charger circuits. Desinged current limiter circuit with tight tolerance for high side protected switch.

Dec 1997 – Apr 2000 · 2 yrs 4 mos · Dallas/Fort Worth Area

• Designed simple analog circuits on technology development testchips for matching characterization of new technologies. Design and verification of technology development testchips for TI, motorola, Chartered Semiconductor and Tower Semiconductor fabs.