Animes D.

Product Engineer

Bengaluru, Karnataka, India5 yrs 7 mos experience

Key Highlights

Led successful STA for advanced SOC designs.
Expert in DVFS optimization and timing closure.
Strong foundation in embedded systems and electronics.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Static Timing Analysis and Physical Design.

Contact

Skills

Core Skills

Static Timing AnalysisPhysical Design

Other Skills

DVFS optimizationTMBISTDFTTCLMicroelectronicsElectronics and communicationLECCLPTweakerTempusSynopsys PrimetimeC (Programming Language)VerilogC++Analytical Skills

About

As a Senior STA Engineer at MediaTek, I lead the Static Timing Analysis (STA) of cutting-edge SOC Macros and Routers, overseeing millions of instances and ensuring optimal timing closure. I utilize advanced techniques such as DVFS optimization and manual fixes, and provide crucial feedback to the Physical Design (PD) team, facilitating continuous improvement. I graduated with a Master of Engineering in Embedded Systems from BITS Pilani Goa Campus in 2022, where I was a part of the Scholars' Club for academic excellence. I also hold a GATE certification issued by IIT Delhi, and multiple Udemy certifications in FPGA Embedded Design and Microcontroller Development. I have a solid foundation in research, design, and development of electronic systems and devices, and have worked in different segments of the communication industry, and in robotics. I have a passion for invention, innovation, and problem-solving, and a goal to contribute to the advancement of technology and society.

Experience

5 yrs 7 mos

Total Experience

1 yr 10 mos

Average Tenure

1 yr 11 mos

Current Experience

Google

Physical Design Engineer

Jul 2024 – Present · 1 yr 11 mos · Bengaluru, Karnataka, India

Mediatek

2 roles

Senior Engineer

Jul 2022 – Jul 2024 · 2 yrs

1. Led the Static Timing Analysis (STA) of cutting-edge SOC Macros and Routers:
Successfully managed STA for a 3nm SOC Macro and a 6nm Router, overseeing millions of instances.
Utilized advanced techniques such as DVFS optimization and manual fixes to ensure optimal timing closure.
Provided crucial feedback to the Physical Design (PD) team, facilitating continuous improvement.
2. SOC Macro STA:
Managed 6.8 million instances across 2 partitions.
Addressed diverse timing issues, including clock transitions and data path optimizations.
Conducted comprehensive 4-mode analysis to refine design performance.
3. Router STA:
Orchestrated STA for 25 million instances across 13 partitions.
Overcame challenges like crosstalk to achieve efficient timing solutions.
Executed rigorous analysis, covering setup/hold timing and data integrity paths.
4. Display Partition Synthesis:
Synthesized a critical partition with 3.2 million instances at 1.4 GHz.
Implemented TMBIST, FUSE & DFT insertion for robust testing capabilities.
Employed innovative synthesis techniques like retiming and register merging to meet stringent timing requirements.
Conducted thorough quality checks including logical equivalence and power integrity assessments.
Overall, contributed significantly to the success of complex semiconductor projects by ensuring timely delivery and high-quality designs.

Static Timing AnalysisDVFS optimizationTMBISTDFTTCLPhysical Design

Intern

Jan 2022 – Jul 2022 · 6 mos

Birla institute of technology and science, pilani - goa campus

2 roles

Teaching Assistant

Nov 2020 – Jan 2022 · 1 yr 2 mos

Students' Representative - Student Faculty Council (SFC)

Nov 2020 – Jan 2022 · 1 yr 2 mos

An active member of the SFC of the Embedded Systems(EEE) Department, BITS Pilani - Goa Campus which interacts with EEE Faculty members and gives feedback regarding courses taught, improvements needed. etc