Apr 2021 – Dec 2025 · 4 yrs 8 mos · Bengaluru · On-site

• Working on SOC chips for wireless applications

Jul 2019 – Mar 2021 · 1 yr 8 mos · Bengaluru Area, India

• worked on Power Management SOC chips

Jan 2019 – May 2019 · 4 mos

• worked on SERDES mixed signal verification

Dec 2017 – Jun 2019 · 1 yr 6 mos

• Workee with Texas Instruments, Silicon and Beyond for Mixed Signal Verification

Dec 2017 – Jan 2019 · 1 yr 1 mo · Bengaluru Area, India

• Power Sequence Block Modelling and verifying Real Number Models in SOCDV environment

Jul 2017 – Nov 2017 · 4 mos · Bengaluru Area, India

• Project-1: SPICE Level Verification of IO Ring Pads
• POC signal is generated by combination of Reset & Enable pins.
• Verified core and the power up sequence of operation.
• Project-2: SPICE level verification of critical path delay for IO rgmii
• This project is for verification of IO rgmii. Critical path delay between flip flops needs to be measured to decide the fastest mode of operation of the core. The simulation is done for different temperature profile and different bias voltages for sequential blocks (flip flop) and combinational circuit (chain of buffers and inverters)
• Develop stimulus for different corners.

Apr 2017 – Jul 2017 · 3 mos · Bengaluru Area, India

• Project Description:
• The Cadence USB 2.0 OTG PHY IP is a hard PHY macro consisting of a single USB 2.0PHY core. This IP is designed to the USB 2.0 specification, and operates at High Speed(480Mbps), Full Speed (12Mbps), and Low Speed (1.5Mbps). The USB 2.0 core complieswith the UTMI v1.05 specification.
• Responsibilities:
• Developed AMS Verification workplan for different modes of operation HS, FS, LS.Developed High Level Modelling (HLM), Modular Level Modelling (MLM), AnalogMixed Signal (AMS) Verification.
• Running testcases

Jul 2016 – Nov 2017 · 1 yr 4 mos · Bengaluru, Karnataka, India

• worked with clients Analog Device, Cadence Design System. Also, was involved in internal projects
• 1. Project: Abstract level model of sigma-delta ADC using Real Number Modelling (RNM)
• Domain: AMS Verification
• Description: Abstract level model was developed.
• 2.Project: Developing a model for a switch & completed UVM Verification
• Domain: UVM Methodology
• Description: Switch is a packet based protocol. Switch drives the incoming packet which comes from the input port to output ports based on the address contained in the packet. The switch has a one input port from which the packet enters. It has four output ports where the packet is driven out.
• 2. Project: Verilog-AMS & WREAL MODELS
• Domain: AMS Verification
• Description: Following models were developed
• Comparator,Clock generator,Flip Flop,Buffer,Signed ADC,DAC,Analog Filter(LPF, BPF,BRF, HPF),Digital Filter(LPF, BPF, BRF, HPF),Amplifier(with SR, BW, ts specs),Power management Blocks DC-DC Converter
• LDO
• 4. Project: Cerebrex Equalizer Modelling
• Domain: Mixed Signal Verification
• Description: Specifications were implemented in MATLAB-SIMULINK and HDL code were realized and
• verification was done using Cadence Incisive.
• 5. Project: Design of unity gain buffer meeting given specification compliance matrix in TSMC 65nm
• technology
• Domain: Analog Design
• Description: Supply=3.3±10%, Temp=-400C-1250C, ICMR=2.4 V±10%,IQ=85μA(max.), Gain
• error=927μV(max.),settling time(max.)=29.4ms, PSR=-56 dB across all corners with Monte Carlo results
• 6. Project: Characterization of MOSFET nch_25ud18 & pch_25ud18 in TSMC 65nm technology
• Domain: Analog Design
• Description: Parameters like FoM, Output & Transfer characteristic, Threshold
• voltage variation with channel L-W-Vdsl-Vbs potential, transconductance variation with Vgs, trans-conductance efficiency, transit frequency variation with Vgs, intrinsic gain variation with gate voltage, second order effects: DIBL, GIDL,and sub-threshold slope, leakage characterization were done.

Jan 2014 – Jul 2016 · 2 yrs 6 mos · Kharagpur Area, India

• PROJECT-1
• Develop schematic to layout of 3 Bit Flash ADC in Cadence virtuoso using UMC 180nm technology
• Specifications :
• DC Characteristic : INL=0.4LSB DNL= +/-0.2LSB
• AC Characteristic : SINAD = 16.162, ENOB=2.4(exclusing parasitics) SINAD= 9.0107 dB,ENOB=1.3 (including parasitics) for fin=3.891 KHz fs=500KHz
• PROJECT-2
• Implemented Blood Pressure Measurement System using LPC 1768 microcontroller and synchronization of data was achieved with smart phone via Bluetooth (RN-42). Our group received second prize from Samsung for best innovation award
• PROJECT-3
• Develop Verilog code (RTL to GDSII) for optimized design of arithmetic adder which can add to ‘N’ where N is the user defined variable. Trade off was made with area to consume minimum power and minimum delay.
• Tools: Synopsys-Design Compiler, Physical Design- IC Compiler
• PDK Used: SAED 90nm technology
• PROJECT-4
• Develop Verilog code for 16 bit pipeline adder with latency of only 3 clock cycles, synthesize and implemented in Xilinx and verified design by System generator in MATLAB.
• Tools: MATLAB, Simulink, System Generator, Xilinx
• PROJECT-5
• Develop Behavioral code for Programmable Booth Multiplier synthesize and implemented in Xilinx
• PROJECT-6
• Design of Programmable Notch filter for attenuating harmonic components. Verilog code synthesize and implemented in Xilinx and verified using System Generator in MATLAB.
• Tools: MATLAB, Simulink, System Generator, Xilinx
• PROJECT-7
• Designed system level design of 12V to 5V DC-DC Buck Converter in MATLAB and transistor level design was done in Cadence (SPICE-schematic). Efficiency was greater than 98%. Phase margin of system was increased to 65 degrees from 14 degrees by PID compensator. Folded cascade op-amp was used for error amplifier having DC gain of 60 dB and phase margin of 80 degree.
• Tools: Cadence-Virtuoso PDK UMC 180nm technology, MATLAB, Simulink

Jun 2012 – Dec 2013 · 1 yr 6 mos · Bhubaneswar, Odisha, India

• SPRING SESSION(JUNE-DEC 2012)
• Lecture Subjects on
• 1. MOSFET Device Modelling
• 2. Semiconductor Devices
• 3. Control System
• AUTUMN SESSION(JAN-JUNE 2013)
• 1. Electromagnetic Theory
• 2. VLSI Design
• 3. Analog Electronic Circuits - II
• SPRING SESSION(JULY-DEC 2013)
• 1. Signal & Network
• 2. Analog Electronic Circuits – I
• 3. Semiconductor Devices
• LAB SESSIONS
• 1. VLSI Design
• Behavioral, Dataflow, Switch Level, Gate Level Modelling style for combinational and sequential circuit description using Verilog
• Implement Design in SPARTRAN Board
• 2. Control System
• Implementation of Proportional(P), Proportional Derivative(PD), Proportional Integral Derivative (PID) Controllers
• 3. Analog Electronic Circuits- I and II
• Opamp circuit design using Tanner EDA tool/ LT Spice, Analog Filter Design