Arpita M. — Software Engineer
ASIC RTL Checks| Lint | CDC | LEC| VCLP | Integration| Digital Design | Verilog| ETHERNET | AXI | FPGA DESIGN FLOW | ASIC Design Flow | Static Timing Analysis| XILINX Vivado | Xilinx SDK environment. Demonstrated various example projects on Zedboard.Adapting myself to TCL scripting, system Verilog.I am comfortable in understanding the hardware schematics, C, C++.
Stackforce AI infers this person is a highly skilled ASIC and digital design engineer with extensive experience in validation and synthesis.
Location: Bengaluru, Karnataka, India
Experience: 5 yrs 9 mos
Skills
- Asic Design Flow
- Digital Design
- Rtl Design
- Asic Quality Check
- Validation
Career Highlights
- Expert in ASIC design and validation processes.
- Proficient in RTL design and quality checks.
- Strong background in digital design and FPGA workflows.
Work Experience
AMD
Senior Silicon Design Engineer (1 yr 11 mos)
Member of Technical Staff (1 yr)
Intel
ASIC Synthesis and validation Engineer (1 yr 8 mos)
Larsen & Toubro Technology Services
RTL design Engineer (3 yrs 10 mos)
Education
BTech - Bachelor of Technology at Silicon Institute of Technology (SIT), Bhubaneswar
