Jul 2023 – Present · 2 yrs 10 mos · Hyderabad · On-site

• Reduce incremental C++ build time by 30% by reorganizing header include paths, improving parallel build consistency across development teams.
• Designed and implemented Vivado config flows command enabling strategy-driven implementation with automatic propagation across opt/place/route stages, eliminating repetitive manual setup and standardizing flows across AMD.
• Built Python-based backup and restore system for message logs spanning multiple subsystems, with schemas managed via PostgreSQL to prevent data loss and improve reliability.
• Reduced XSA generation time by 40% through GDB profiler analysis and targeted performance tuning, directly improving throughput for the entire FPGA design team.
• Developed automation commands for Vivado project regeneration, optimized for multithreaded execution to enhance productivity.
• Designed early-detection mechanisms for syntax and compilation issues during RTL parsing, reducing debugging time.
• Migrated Vivado automation workflows from TCL and GUI to Python mode using C++, improving maintainability
• and scalability.
• Implemented automated cleanup of intermediate FPGA design artifacts to prevent race conditions in concurrent development flows.
• Maintained and enhanced HSI module with thread-safe improvements, ensuring reliability in multi-threaded environments.
• Resolved complex hardware-related HSI issues in collaboration with cross-functional teams, improving system stability.
• Enabled seamless hardware-software co-design and integration using Vivado, XSCT, and XSA.
• Architected and added new hardware interface features to XSA, expanding system capabilities.
• Developed comprehensive unit tests for 37 HSI APIs, improving concurrency correctness and test coverage.
• Enhanced debugging workflows and implemented improved DRC mechanisms to catch errors earlier in the development cycle.
• Resolved critical bugs during Vivado release cycles, ensuring product stability and meeting release deadlines.