Devansh Saxena

Software Engineer

Bengaluru, Karnataka, India8 yrs 7 mos experience
Highly Stable

Key Highlights

  • Senior Physical Design Engineer at Nvidia.
  • Expertise in Verilog and FPGA design.
  • Strong foundation in Electronics and Communications Engineering.
Stackforce AI infers this person is a VLSI and Embedded Systems Engineer with strong FPGA and digital design skills.

Contact

LinkedIn

Skills

Core Skills

VerilogFpgaDigital Design

Other Skills

C++Vivado HLSCHTMLSQLMatlabLinuxXilinx Vivado HLSPerlPythonVivado IDESTA

Experience

8 yrs 7 mos
Total Experience
2 yrs 11 mos
Average Tenure
3 mos
Current Experience

Nvidia

Senior Physical Design Engineer

Feb 2026 – Present · 3 mos · Bengaluru, Karnataka, India

C++Vivado HLSVerilogCHTMLSQL+6

Synopsys inc

Staff Engineer

Jul 2025 – Feb 2026 · 7 mos · Bengaluru, Karnataka, India

  • Continuing my role from Ansys after Synopsys acquisition.

Ansys

3 roles

Senior Product Specialist

Promoted

Apr 2025 – Feb 2026 · 10 mos · Bengaluru, Karnataka, India

Product Specialist II

Apr 2023 – Apr 2025 · 2 yrs · Bengaluru, Karnataka, India

Product Specialist

Jul 2021 – Apr 2023 · 1 yr 9 mos · Bengaluru, Karnataka, India

Delhi technological university (formerly dce)

Summer In-House Training

Jun 2020 – Jul 2020 · 1 mo · Delhi, India

  • Implemented Built in Self-Test (BIST) using Verilog on Vivado IDE.
  • BIST circuit for 8-bit ripple carry adder using modified LFSR as test pattern generator and MISR as output response analyser. Gray code counter was used to minimise switching activity and hence reduce power consumption.

3st technologies

Winter Training

Dec 2019 – Jan 2020 · 1 mo · Noida, Uttar Pradesh

  • VLSI Course:
  • Digital Design
  • Verilog
  • STA
  • Linux
VerilogLinux

Skyfi labs

Project Trainee

Jan 2019 – Mar 2019 · 2 mos · Delhi, India

  • Arduino Projects Course
  • 1) Animatronic Hand
  • 2) Solar Tracker
  • 3) Persistence of Vision
  • 4) Vehicle Tracking System
  • 5) Smart Energy Meter
Digital DesignVerilogSTALinux

Hindustan petroleum corporation limited

Summer Intern

Jun 2018 – Jul 2018 · 1 mo · Delhi Area, India

  • HPCL Network Infrastructure, Connectivity & Devices.

Ieee dtu

Member

Aug 2017 – May 2021 · 3 yrs 9 mos · New Delhi Area, India

Education

Delhi Technological University (Formerly DCE)

Bachelor of Technology - BTech — Electronics and Communications Engineering

Jan 2017 – Jan 2021

Kendriya Vidyalaya

Jan 2011 – Jan 2017

Our Lady of Perpetual Succour, High School, Mumbai

Jan 2005 – Jan 2011

Stackforce found 100+ more professionals with Verilog & Fpga

Explore similar profiles based on matching skills and experience

VIKAS PATEL

VIKAS PATEL

Senior Software Engineer(Timing Closure)

at AMD

Dhanbad, India4 yrs 11 mos exp
Hardware Emulation
NP

Nirav Patel

Analog Design Sr Staff Engineer

at Synopsys Inc

Bengaluru, India12 yrs 9 mos exp
Analog Circuit DesignDigital Circuit Design
Shashidhara K S

Shashidhara K S

Engineer, Senior

at Qualcomm

Bengaluru, India12 yrs 8 mos exp
ASIC DesignRTL Design
Vivek Sheel Mittal

Vivek Sheel Mittal

SoC Architect

at Qualcomm

Bengaluru, India23 yrs 6 mos exp
SoCASIC
Nonie Politi

Nonie Politi

FPGA Developer

at Hudson River Trading

Singapore, Singapore16 yrs 7 mos exp
Digital Circuit DesignEmbedded Systems DesignFPGA DevelopmentResearch and Development
Mohit Negi

Mohit Negi

System Engineer

at Intel Corporation

Greater Delhi, India14 yrs 3 mos exp
SimicsComputer System ValidationPlatform ArchitectureC++
Sanyam Jain

Sanyam Jain

Lead Engineer (FPGA)

at Logic Fruit Technologies

Gurugram, India3 yrs 11 mos exp
JT

Jeebu Jacob Thomas

FPGA Engineer

at VivCourt Trading Pty Ltd

Sydney, Australia15 yrs 3 mos exp
FPGADigital DesignHigh Frequency TradingHigh Level SynthesisHigh Performance Computation