Ashutosh Rao — Software Engineer

I design silicon and build intelligent automation to make chip design smarter, faster, and more efficient. Currently, I am an R&D Engineer in the Foundational IP group at Synopsys, where I contribute to the Logic Library Test Chip team. My role spans circuit design, design analysis, STA, PPA optimization, and pre/post-silicon validation, along with developing automation and AI-driven engineering workflows that enhance productivity and insight. My core strength lies at the intersection of hardware and intelligence. With proficiency in Verilog, SystemVerilog, and Python, I enjoy architecting robust digital systems and building tools that augment engineering through automation and AI agents. I am particularly interested in advancing how intelligent systems can transform traditional VLSI design and validation methodologies. Alongside my professional work, I have been actively involved in leadership roles and community building. I served as Student Head of PES Innovation Lab and contributed as a core member of the IEEE RAS Student Chapter at PES University, where I helped foster innovation and collaboration. I am driven by a long-term vision to contribute to next-generation semiconductor design by combining deep hardware expertise with intelligent automation. I am always open to connecting with engineers, researchers, and innovators working on challenging problems in VLSI, hardware systems, and AI-driven chip design :)

Stackforce AI infers this person is a Semiconductor Engineer specializing in VLSI design and AI-driven automation.

Location: Bengaluru, Karnataka, India

Experience: 4 yrs 4 mos