Ashwini Saikiran

Software Engineer

Telangana, India5 yrs 6 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Experienced in ASIC digital design and verification.
  • Proficient in SystemVerilog and formal verification techniques.
  • Strong background in embedded systems and IoT applications.
Stackforce AI infers this person is a Digital Design Engineer with expertise in ASIC and embedded systems.

Contact

Skills

Core Skills

SystemverilogFormal Verification

Other Skills

VerilogDigital ElectronicsC (Programming Language)Data StructuresProgrammingPrinted Circuit Board (PCB) DesignPython (Programming Language)MATLABWindowsEmbedded SystemsInternet of Things (IoT)Electronic Circuit Design

Experience

5 yrs 6 mos
Total Experience
1 yr 8 mos
Average Tenure
3 yrs 9 mos
Current Experience

Synopsys inc

2 roles

ASIC Digital Design, Sr Engineer

Promoted

Jan 2024Present · 2 yrs 5 mos

SystemVerilogFormal VerificationVerilogDigital ElectronicsC (Programming Language)Data Structures+8

ASIC Digital Design, Engineer

Aug 2022Dec 2023 · 1 yr 4 mos

Formal VerificationSystemVerilog

Nvidia

Hardware Intern

Jan 2022Jun 2022 · 5 mos

Formal VerificationSystemVerilog

Training & placement cell, nit sikkim

2 roles

ECE Departmental Coordinator

Jul 2021Jul 2022 · 1 yr

Volunteer

Oct 2020Jul 2021 · 9 mos

Swayam mhrd

Hardware Modeling using Verilog

Jun 2021Jul 2021 · 1 mo

Anuvrat

2 roles

Resource Management Lead

Promoted

Apr 2021Jul 2022 · 1 yr 3 mos · Ravangla, Sikkim, India

Member

Feb 2021Apr 2021 · 2 mos · Ravangla, Sikkim, India

Navica communications pvt ltd

Embedded, IoT Application Design and Testing

Dec 2020Feb 2021 · 2 mos

Engecture.in

Printed Circuit Board Designing

Jul 2020Aug 2020 · 1 mo

Education

National Institute Of Technology Sikkim

B. Tech — Electronics and communication

Jan 2018Jan 2022

Stackforce found 100+ more professionals with Systemverilog & Formal Verification

Explore similar profiles based on matching skills and experience