Asit Verma

CTO

Bengaluru, Karnataka, India18 yrs 7 mos experience

Highly Stable

Key Highlights

17 years of experience in power and performance optimization.
Expert in pre-silicon and post-silicon optimizations.
Proven track record in architecting power-efficient solutions.

Stackforce AI infers this person is a Power and Performance Architect with expertise in semiconductor and mobile technology.

Contact

Skills

Core Skills

Power And PerformanceArchitectureSystem ValidationDebugging

Other Skills

Embedded SystemsComputer ArchitectureProject ManagementOptimizationsSilicon ValidationPnP optimizationsKPI definitionsRoot causingFunctional failuresPower OptimizationsPerformance BenchmarkingLow Power MeasurementLinux KernelInstrumentationPerl

About

Asit has a 17 years of experience in area of power and performance including pre silicon and post silicon PnP optimizations , architect and product planning.

Experience

18 yrs 7 mos

Total Experience

6 yrs 3 mos

Average Tenure

6 mos

Current Experience

Google

Soc Architect

Dec 2025 – Present · 6 mos · Greater Bengaluru Area · On-site

Engineering manager, Power and Performance

DebuggingEmbedded SystemsComputer ArchitectureProject ManagementOptimizationsPower and Performance+1

Qualcomm

GPU Product Planner and Performance architect

Jun 2023 – Mar 2026 · 2 yrs 9 mos · Bengaluru, Karnataka, India · On-site

Intel corporation

4 roles

Technical Lead

Oct 2015 – Nov 2023 · 8 yrs 1 mo

Delivering power , performance and responsiveness on Intel core mobile platforms

Power and PerformanceSilicon ValidationOptimizationsArchitecture

Connectivity Power & Performance Engineer

Promoted

Jun 2014 – Sep 2015 · 1 yr 3 mos

WWAN use cases PnP optimizations and KPI definitions
WLAN use cases PnP optimizations and KPI definitions
GPS use cases PnP optimizations and KPI definitions
BT/NFC use cases PnP optimizations and KPI definitions
for Intel tablet platforms

Power and PerformancePnP optimizationsKPI definitionsArchitecture

System Validation Engineer

Jan 2013 – May 2014 · 1 yr 4 mos

Full Chip Debug Engineer
Root causing silicon and platform issues of greater complexities
Issues involves various IPs from South cluster, storage comms, USB3, audio , security , Intel legacy IPs, modem, pmic, wifi, Bluetooth, interconnect fabrics, Dfx and others.
Root causing, providing workaround and resolution for various functional failures of android use cases.

DebuggingRoot causingFunctional failuresSystem Validation

Platform Power and Performance Engineer

Jul 2009 – Dec 2012 · 3 yrs 5 mos

Delivered Power & Performance optimizations on six generation of platforms
Low Power Instrumentation
Low Power Measurement, Methodologies and Analysis
Power Optimizations for standby Use cases
Power Optimizations for Media Use cases
Power and Performance Board requirements
Power Automation requirements
Performance Benchmarking
Creating Optimization Plans and driving it to meet pre silicon estimates
Power and Performance projections for smartphone and tablet platforms for various android and meego use cases
Overall platform power efficiency improvements including efficiency optimizations for platform power delivery chip
Display power projections and driving first time use cases of Display self refresh and achieving best power targets in industry for smartphones
Silicon part characterization say of slow, fast typical parts and come up with platform power ranges for android use cases to be seen on products in market
Defining and Enabling key power and performance indicators
Power and performance optimizations done for first Intel android smartphone and tablet products