Athiya Nizam

Product Engineer

Austin, Texas, United States7 yrs 6 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

6+ years of experience in the semiconductor industry.
Expertise in testing and validation for Xeon Server products.
Strong educational background with a Master's in Electrical Engineering.

Stackforce AI infers this person is a Semiconductor Validation Engineer with expertise in testing and data analysis.

Contact

Skills

Core Skills

TestingData AnalysisValidation TestingFirmware DevelopmentTeachingResearch

Other Skills

Post Silicon HVM bring uptest program content developmentclass level ATE test flowThermal/DTS test methodologypre-silicon simulationstandardized scripts/toolsPCIe platform/system validationElectrical validation testingFirmware updateVoltage-Frequency Curve analysisPCIe Express characterizationMentoringLab measurementStability determinationReliability analysis

About

6 + years of experience with demonstrated skills of working in the semiconductor industry. Strong engineering professional with a Master's degree focused in Electrical Engineering (Major VLSI) from University of Missouri-Kansas City.

Experience

7 yrs 6 mos

Total Experience

3 yrs 9 mos

Average Tenure

6 yrs 3 mos

Current Experience

Intel corporation

4 roles

Product Engineer

Oct 2022 – Present · 3 yrs 8 mos

Product Engineer

Apr 2022 – Sep 2022 · 5 mos

Product Development Engineer

Jan 2020 – Mar 2022 · 2 yrs 2 mos

Post Silicon HVM bring up and test program content development for latest Xeon Server products for DTS/Thermal ip
Experience in developing and executing class level ATE test flow. Testing the product from wafer sort level to class and PPV to screen out defects and take the product to PRQ by implementing optimal solutions
Maintaining standardized scripts/tools to enhance overall productivity and effectiveness
Pre-silicon simulation using simulation tools to catch bugs before tape-out
Implementing Thermal/DTS test methodology at different sockets and performing data Analysis of volume data using JMP to post process the results obtained during test flow

Post Silicon HVM bring uptest program content developmentclass level ATE test flowdata AnalysisThermal/DTS test methodologypre-silicon simulation+3

Graduate Technical Intern

Sep 2019 – Dec 2019 · 3 mos

Performing PCIe platform/system and electrical validation testing for PCIe SSD
Firmware update on SSD. Execution of Electrical validation plans TX, RX compliance, equalization and ensure performance meets to PCI SIG specifications

PCIe platform/system validationElectrical validation testingFirmware updateValidation TestingFirmware Development

Marvell semiconductor

Silicon Validation Intern

Jun 2019 – Aug 2019 · 2 mos · Santa Clara, California

Collected and analyzed voltage, frequency and temperature data using data analysis tools across PVT corners
Voltage-Frequency Curve analysis with improvement in yield and power management for ThunderX2 Server Processors
PCIe Express 3 characterization and signal quality testing across PVT corners at TX.

Data analysisVoltage-Frequency Curve analysisPCIe Express characterizationData AnalysisValidation Testing

University of missouri-kansas city

3 roles

Graduate Teaching Assistant

Aug 2018 – May 2019 · 9 mos

Signals and Systems Lab :
Mentor students and provide academic support to engineering undergraduates in the lab for the course
Evaluate and grade examinations, assignments and homework's.
Coordinate with Professors and fellow Teaching Assistants for a continuous assessments and improvements to help students
Electronic Circuits Laboratory:
Lab measurement and data analysis using lab equipment’s like oscilloscopes, signal generators and multi-meters.
Pspice and MATLAB analysis of lab experiements also done.
HDL ( Verilog ) Laboratory

MentoringLab measurementData analysisTeachingData Analysis

Graduate Student Assistant

Feb 2018 – May 2018 · 3 mos

*Introduction to Computer Architecture

Graduate Research Assistant

Jan 2018 – May 2019 · 1 yr 4 mos

Determined the stability of SRAM cells in HSpice at different process corners and determined the reliability of cell: butterfly curve, N-curve, and Monte Carlo analysis.
7 nm PDK FinFET and 7nm Asymmetrical underlapped FinFET based 6T and 8T SRAM cell design
Comparing performance metrics by calculating RSNM, HSNM, WSNM, leakage power and delay using HSPICE

Stability determinationReliability analysisPerformance metrics calculationResearchData Analysis