Ayush Bhardwaj

Software Engineer

Ghaziabad, Uttar Pradesh, India3 yrs 10 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in Analog and Mixed Signal Circuit Design.
Proficient in multiple technodes from 180nm to 8nm.
Hands-on experience with FPGA and ASIC design.

Stackforce AI infers this person is a VLSI Design Engineer with expertise in Analog and Mixed Signal Circuit Design.

Contact

bhardwajayush02@gmail.com LinkedIn

Skills

Core Skills

Analog And Mixed Signal Circuit DesignLayout DesignFpga Design

Other Skills

ALU DesignAnalog Circuit DesignAnalog LayoutApplication-Specific Integrated Circuits (ASIC)Arduino IDEBCD counterBootstrap switchC (Programming Language)CAP DACCadence VirtuosoCadence Virtuoso Layout EditorChip level ESDCombinational CircuitsDC-DC ConverterDRC

About

I am an experienced Analog and Mixed Signal Circuit Design and Layout having an experience of more than 3 years. My expertise includes: - Responsible for Test Chips Layout and Different IP's in different technodes(180nm,110nm,55nm,22nm,8nm) Layout with Delivery Database and Packaging Doc along with complete verification (LVS,DRC, Post Layout Simulations). - Responsible for Designing and layout of 16M On-Chip RC Relaxation Oscillator along with complete verification. - Responsible for Layout of SAR ADC, Sigma Delta ADC, High Speed Input Buffer, Bootstrap switch, Different Opamps, CAP DAC, Temperature Sensor , DC-DC Converter along with complete verification. - Responsible for resolving Chip level ESD, Antenna, Latch-up along with complete Chip level Power mesh and Decaps. - Knowledge of Layout Reliability Issues like Electromigration, Latch-up, Fingering, Multipliers, Antenna Effect, Well Proximity, Matching, ESD, Shielding, IR Drop,Deep Nwell, LOD effect. - Knowledge of Analog Concepts. - Knowledge of UNIX Commands. - Knowledge of Digital Design Concepts.

Experience

3 yrs 10 mos

Total Experience

3 yrs 10 mos

Average Tenure

3 yrs 10 mos

Current Experience

Vervesemi

3 roles

Design Engineer II

Promoted

Jul 2024 – Present · 1 yr 11 mos

Responsible for Test Chips Layout and Different IP's in different technodes(180nm,110nm,55nm,22nm,8nm) Layout with Delivery Database and Packaging Doc along with complete verification (LVS,DRC, Post Layout Simulations).
Responsible for Designing and layout of 16M On-Chip RC Relaxation Oscillator along with complete verification.
Responsible for Layout of SAR ADC, Sigma Delta ADC, High Speed Input Buffer, Bootstrap switch, Different Opamps, CAP DAC, Temperature Sensor , DC-DC Converter along with complete verification.
Responsible for resolving Chip level ESD, Antenna, Latch-up along with complete Chip level Power mesh and Decaps.

Test Chips LayoutIP LayoutLVSDRCPost Layout SimulationsRC Relaxation Oscillator+13

Design Engineer

Aug 2022 – Jul 2024 · 1 yr 11 mos

Design Engineer Trainee

May 2022 – Aug 2022 · 3 mos

Pine training academy

2 roles

ASIC Design and Full Custom Layout Trainee

Sep 2021 – May 2022 · 8 mos · Ghaziabad, Uttar Pradesh, India

FPGA Design Trainee

Aug 2020 – Oct 2021 · 1 yr 2 mos · Ghaziabad, Uttar Pradesh, India

Knowledge of Verilog Hardware Description Language
Knowledge of VHDL Hardware Description Language
=> ALU Design
=> Odd/Even parity bit Generator
=> Digital Stopwatch on FPGA Board Artix-A7
=> Pine project with timer on FPGA Board Artix-A7
=> BCD counter on FPGA Board Artix-A7
4-bit signed calculator on FPGA Board Artix-A7
Schematics design of Digital logic circuits implemented on FPGA Board Artix-A7

VerilogVHDLALU DesignDigital StopwatchBCD counterSchematics design+1

Innerve

Campus Ambassador

Oct 2020 – Nov 2020 · 1 mo

Ieee iiit-delhi student branch

Campus Ambassador

Sep 2020 – Oct 2020 · 1 mo

Techfest, iit bombay

Campus Ambassador

Jul 2020 – Jan 2021 · 6 mos · Mumbai, Maharashtra, India

National institute of electronics & information technology (nielit)

VLSI Design

Jun 2020 – Jun 2020 · 0 mo · Gorakhpur, Uttar Pradesh, India

PSpice simulation of MOSFET based circuits
Knowledge of Verilog and VHDL Language
Hands on Model Sim Tool
ALU Design Project

PSpiceVerilogVHDLModel Sim

Pine training academy

Digital Design Trainee

Aug 2019 – Jun 2020 · 10 mos · Delhi NCR

Hands-on Xilinx ISE tool
Hardware Design of 4-Bit Signed Binary Calculator
=> 4-bit Signed Adder
=> 4-bit Signed Subtractor
=> 4-bit Signed Multiplier
=> 4-bit Signed Divider
Schematics design of Combinational and Sequential circuits

Xilinx ISEHardware DesignCombinational CircuitsSequential Circuits

Education

Indian Institute of Technology, Roorkee

Master of Technology - MTech — VLSI

Jul 2024 – Present

KIET Group of Institutions

Bachelor of Technology - BTech — Electronics and Communications Engineering

Aug 2018 – Jul 2022

Delhi Public School Ghaziabad

12

Jan 2016 – Jan 2017

Mount Carmel School Muradnagar

10

Jan 2014 – Jan 2015

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