Ayushi Sharma — Software Engineer
DFT Design Engineer with an experience of 2.5 Year. Handled the following responsibilities: ● MBIST and BSCAN Insertion for Chip level ●MBIST pattern generation and simulation ●Edited DFT specification according to project requirement ●Debugged DRC violation in Atpg and Mbist ●Implemented Pin Muxing logic to switch between different modes ●Logic Equivalence Checks ●Generated and simulated patterns for parallel stuckat and serial stuckat (ATPG) ●Simulated patterns in mbist for slow bist and fast bist mode ●Timing Simulations ● Tessent Diagnosis ●Generated patterns for different modes ●Coverage Analysis on all modes
Stackforce AI infers this person is a DFT Engineer with expertise in digital design and testing methodologies.
Location: Ghaziabad, Uttar Pradesh, India
Experience: 3 yrs 8 mos
Skills
- Dft
- Static Timing Analysis
Career Highlights
- Experienced in DFT methodologies and ATPG.
- Proficient in Verilog and Static Timing Analysis.
- Strong background in Digital Electronics and Linux.
Work Experience
Synopsys Inc
Senior DFT Engineer (1 yr 7 mos)
Tecquire Solutions Pvt Ltd
DFT Design Engineer (2 yrs 1 mo)
PinE Training Academy
DFT Trainee (4 mos)
Bharat Electronics Limited
Internship Trainee (2 mos)
Education
Bachelor of Technology - BTech at Inderprastha Engineering College
