Bhanuja Upadhyay

CEO

Bengaluru, Karnataka, India8 yrs 2 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in Physical Design and Verification
Proficient in leading design projects
Strong background in VLSI methodologies

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Physical Design and Verification.

Contact

Skills

Core Skills

Physical DesignPhysical Verification

Other Skills

ICCPSpiceVerilogXilinxModelSimCoding VerilogSynopsys PrimetimeSystemVerilogPerlLinuxCadence VirtuosoVery-Large-Scale Integration (VLSI)Cadence Encountersynopsys IC compilerplace and route

Experience

8 yrs 2 mos

Total Experience

2 yrs 8 mos

Average Tenure

7 yrs 3 mos

Current Experience

Cadence design systems

2 roles

Lead Solutions Engineer

Promoted

Jul 2022 – Present · 3 yrs 11 mos

Physical designphysical verificationICCPSpiceVerilogXilinx+16

Senior Application Engineer

Feb 2019 – Jun 2022 · 3 yrs 4 mos

Qualcomm

Physical Design Engineer

May 2018 – Nov 2018 · 6 mos · Bengaluru Area, India

Done Floorplanning, PnR, CTS, Route, PV, STA, FV on a block. (netlist to GDS)

FloorplanningPnRCTSRoutePVSTA+2

Amd

PV CAD Engineer

Dec 2017 – May 2018 · 5 mos · Bengaluru

Worked from Insemi tech. as PV trainee engineer and has experience in Calibre for Physical verification and scripting.

CalibrePhysical verificationscripting

Chipedge technologies pvt ltd

Physical Design Trainee

Dec 2017 – Mar 2018 · 3 mos · Bengaluru, Karnataka, India

COURSE OUTLINE
VLSI Fundamentals, CMOS Basics, Floor Planning, Power Planning, Placement, clock tree synthesis, Routing, timing analysis & Optimization, Physical Verification, ECO flow.
Tools Used in Training: IC-Compiler, Star-RC, IC Validator, Prime Time.
Project Experience:
Technology / Layers : 28nm / 9 Metal Layers.
Gate count / Area : 731376/ 1195801.62 um 2
Macros : 20
STD Cells : 200075
No. of Clocks : 3
Frequency : 172.4 MHz
Tools Used : IC-Compiler, Star-RC, IC Validator, Prime Time.
Role : To perform Sanity checks, Floor Plan, Power Plan, Placement, CTS, Detail Routing, Timing Analysis & Optimization, DRC, LVS.