Jul 2024 – Dec 2025 · 1 yr 5 mos · Bengaluru, Karnataka, India

Dec 2023 – Jul 2024 · 7 mos

Jun 2022 – Dec 2023 · 1 yr 6 mos

• Responsible for FloorPlan and PnR of latest ARM cores on cutting-edge sub-10nm tech nodes.

Nov 2021 – May 2022 · 6 mos

• 1. Responsible for Power sign-off, Optimization and analysis for CPUSS for MSM and MDMs.
• 2. Deep dive with post Si teams to understand/analyze split parts data for process impact on IddQ(ON/OFF), Vmin and Fmax.
• 3. Responsible for proposing changes to existing methodologies pre Si to enable accurate power modelling across post Si platforms, Thermal, DoU and PDN Peak Powers.
• 4. Cross team knowledge exchange.
• 5. Responsible for cost-effective buck estimate considering Ipeak/Performance trade-off.
• 6. Worked on DCD sign-off, cellEM sign-off and cross corner STA for one project to extend bounds.
• MENTORSHIP
• Ramped Up and mentored few team members from scratch for enabling multiple power deliverables for different projects.

Nov 2019 – Oct 2021 · 1 yr 11 mos

• 1. Worked in Power Estimation/Budgeting, Power Analysis and Optimization of Snapdragon CPUs which are part of QC MSMs and MDMs.
• 2. Worked across multiple tech nodes and owned Power for various CPUs.
• 3. Have good VLSI knowledge and helped in improving power through feedback.
• 4. Involved in the product life cycle from recommending the product spec in terms of power and deriving competitive power targets considering Performance-Power tradeoff to Post Si power correlation.
• 5. Responsible for CPUSS PPA analysis and Power signoff.
• 6. Expertise in PTPX.
• 7. Responsible for enabling CPU PDN for static and Dynamic IR analysis. Helped SoC and software teams for their analysis through feedback and accurate power modelling across multiple DCVS modes.
• 8. Responsible for Thermal signoff - Enabling fine grain thermal analysis along with Performance Benchmarks.
• 9. Owner of CPU Power Model which models the expected CPU design power estimates at various PVTs.
• 10. Responsible for establishing post-Si Power Correlation and identifying the gaps, if any, for multiple scenarios including active and idle modes.
• 11. Responsible for assessing vector scenarios fir for analysis of a particular problem statement like DoU, Thermal, IR drop etc.,

Jul 2018 – Nov 2019 · 1 yr 4 mos

• 1. Joined Qualcomm as CPU Power sign-off Engineer.
• 2. Understanding of RTL to GDS flow.
• 3. Ramped up on Power Analysis for CPU subsystem and continued as CPUSS power sign-off engineer.

May 2017 – Jul 2017 · 2 mos · Bengaluru Area, India