CHETAN ANGADI — Product Engineer
RTL Design Engineer with 2+ years of experience in Memory PHY (HBM3/HBM4) development. Hands-on in Verilog RTL design for timing-critical control logic, including DLL, DCC, DCDL, and regulator control logic. Strong foundation in clocking, calibration FSMs.
Stackforce AI infers this person is a Digital IC Design Engineer with a focus on Memory PHY development.
Location: Bengaluru, Karnataka, India
Experience: 2 yrs 9 mos
Skills
- Digital Ic Design
- Asic
Career Highlights
- 2+ years in Memory PHY development.
- Expertise in Verilog RTL design for control logic.
- Strong foundation in clocking and calibration FSMs.
Work Experience
NVIDIA
Application Specific Integrated Circuit Design Engineer (1 mo)
Cadence Design Systems
Design Engineer I (2 yrs 8 mos)
Rambus
AMTS Logic Design (1 mo)
Logic Design Intern (5 mos)
Education
BE at RV College Of Engineering
at Jawahar Navodaya Vidyalaya - JNV
