C

Chetan Padharia

Software Engineer

Bengaluru, Karnataka, India8 yrs 9 mos experience
Highly Stable

Key Highlights

  • Experienced in Physical Design and SoC Design.
  • Proficient in Static Timing Analysis and Synopsys tools.
  • Strong background in microelectronics and electronics engineering.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Physical Design and SoC methodologies.

Contact

LinkedIn

Skills

Core Skills

Static Timing AnalysisSoc Design

Other Skills

Synopsys PrimetimePrimetimePhysical DesignPNRTCLSynopsys Design CompilerConformal LECSynopsys IC CompilerVerilogXilinx ISECadence VirtuosoPCB DesignCloud ComputingResearchMatlab

About

To secure a challenging position in an organization, where I get an opportunity to utilize my talent, skills and also implement and influence my creative ideas in an organization where there is ample scope and growth for organizational as well as individual development.

Experience

8 yrs 9 mos
Total Experience
2 yrs 5 mos
Average Tenure
1 yr 6 mos
Current Experience

Google

Physical Design Engineer

Dec 2024 – Present · 1 yr 6 mos

Arm

Design Engineer

May 2023 – Dec 2024 · 1 yr 7 mos · Bengaluru, Karnataka, India

Intel corporation

2 roles

SoC Design Engineer

Jun 2019 – May 2023 · 3 yrs 11 mos

Synopsys PrimetimeStatic Timing AnalysisSoC Design

Intern

Jun 2018 – May 2019 · 11 mos

Synopsys PrimetimeStatic Timing AnalysisSoC Design

Tata consultancy services

Assistant System Engineer-Trainee

Aug 2015 – Jun 2016 · 10 mos · Empire Plaza- Vikhroli, Mumbai

  • Developer

Education

Manipal Institute of Technology

Master of Technology - MTech — Microelectronics

Jan 2017 – Jan 2019

University of Mumbai

Bachelor of Engineering (BE) — Electronics Engineering

Jan 2011 – Jan 2015

T.J. High School

Jan 2003 – Jan 2009

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