DEEPAK KUMAR

CEO

Bengaluru, Karnataka, India13 yrs 3 mos experience

Highly Stable

Key Highlights

Expert in UVM-based SystemVerilog design verification.
Strong background in low-power design and ARM architectures.
Proficient in hardware design and validation for SSDs.

Stackforce AI infers this person is a Hardware Design Engineer specializing in complex SoC and SSD architecture.

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Skills

Core Skills

Design VerificationHardware DesignSystem-level VerificationValidationElectrical DesignTesting And Verification

Other Skills

Cortex-ARISC-VCoresighttest benchesARMSSsynthetic bootcodeSystem VerilogUVMbare metal validationLPDDRxx technologyregression flowsPower Circuitry DesignSpice-SimulationsAllegro-Design EntryM.2 SSD

About

Experienced Electrical Design Engineer with a demonstrated history in the computer hardware industry, specializing in hardware design, validation, and system-level verification. Skilled in UVM-based SystemVerilog design verification, bare-metal flow setup, and compile infrastructure development from the ground up. Hands-on expertise across ARM and RISC core architectures, low-power design, and CoreSight debug and trace technologies. Proficient in computer architecture, regression enablement, and functional/performance validation of complex SoC and subsystem designs. Strong exposure to SSD architecture, manufacturing, and lifecycle analysis, with a deep understanding of the intersection between design, validation, and productization. Driven by a passion for building efficient, reliable, and scalable hardware systems. Bachelor’s Degree in Electronics, and Communications Engineering from National Institute of Technology, Tiruchirappalli

Experience

13 yrs 3 mos

Total Experience

2 yrs 9 mos

Average Tenure

2 yrs

Current Experience

Arm

Principal Engineer

Jun 2024 – Present · 2 yrs · Bengaluru, Karnataka, India · On-site

Amazon

Design Verification Engineer

Jun 2022 – Jun 2024 · 2 yrs · Bengaluru, Karnataka, India

Worked on Cortex-A, RISC-V, Coresight components.
Developed test benches for the above components.

Cortex-ARISC-VCoresighttest benchesDesign VerificationHardware Design

Intel corporation

2 roles

Design Verification Engineer

Oct 2020 – Jun 2022 · 1 yr 8 mos

Verification of ARMSS. Setting up synthetic bootcode and setup to enable bare metal content.
Have working knowledge of System Verilog and UVM.

ARMSSsynthetic bootcodeSystem VerilogUVMDesign VerificationSystem-Level Verification

Pre/Post Silicon Validation

Jan 2018 – Oct 2020 · 2 yrs 9 mos

Working on bare metal validation framework development and cpu(ARM core - AXX series) validation( emulation and post silicon ). Have worked on LPDDRxx technology to perform functional/electrical validation. Have expereince in enabling regression flows to ensure automated test of content developed for bare metal.

bare metal validationLPDDRxx technologyregression flowsValidationHardware Design

Seagate technology

Electrical Design Engineer II

Jul 2013 – Jan 2018 · 4 yrs 6 mos · bangalore

Power Circuitry Design of SSD
Designed dc-dc regulators followed by Spice-Simulations and implemented them in schematics using Allegro-Design Entry tool
Designed Power Up Sequencing cicruit
Verification of M.2 SSD and Design of Carrier Card
Simulated Carrier Card and M.2 for Power Delivery using Or-Cad Capture
Board bring up and initial regression test of M.2’s Hardware
Verification of Data Path of M.2 from host via Carrier Card
Verification of Regulators in M.2 and Carrier Card
Calibration of Temperature Sensor, Current and Voltage Monitor on Carrier Card
Thermal Characterization of the Hardware
Hardware Testing and Verification
Test and debug of dc-dc regulators, e-Fuse
Verification of following interfaces: UART, JTAG,PCIe
Verification of Data Hardening during Power down scenarios
Verification of Crystals, Oscillators
Design of Electronic Load with high slew rate
Test Board for Automation of Switch and USB to UART
Scripting Experience
Automation for editing Schematics in Allegro Design Entry HDL using Python
Python was used as a programming language to automate Derating
With the help of Python, scripts were written for BOM comparison
Wrote a script for data collection from a Super cap-Manager interfaced to a NytroWarp Drive card using Python and Raspberry-Pi over I2C interface
Implementation of a Hardware Switch using discrete and analog components and interfaced it with Raspberry-Pi using Python over I2C interfaces
Development, verification and automation of testing process
Development of driver for Oscilloscope, Power Analyser and Electronic Load.
Full ownership for Development and testing of Python codes for testing voltage regulators for following test cases : Timing Analysis, Load and Line Regulation
Designed a HyperTerminal in order to establish link between processor on SSD and host machine

Power Circuitry DesignSpice-SimulationsAllegro-Design EntryM.2 SSDPower DeliveryPython+2

Nit trichy

2 roles

ULTRA LOW POWER SAR-ADC using 180nm technology

Jan 2013 – May 2013 · 4 mos · Tiruchchirappalli Area, India

The project was meant to design an ULTRA LOW POWER SAR-ADC using 180nm technology.

wrapper for on chip buses viz. OCP,AMBA,

May 2012 – Jun 2012 · 1 mo · Tiruchchirappalli Area, India

The project was meant to develop wrapper modules for on chip buses namely AMBA, OCP. The wrapper module takes care of the possible ways in which communication can be done. In asynchronus module we have worked on asynchronus FIFO. Full and empty conditions of FIFO were exploited

Indian institute of technology, guwahati

design of decibel meter

May 2011 – Jun 2011 · 1 mo · Guwahati Area, India

The problem was to design a decibel meter for sound intensity measurement. Have worked on precision rectifier (for mili-volt level signal), used a silicon diode to make a log amplifier, designed a voltage controlled oscillator to convert analog signal to digital level and finally a TTL level frequency meter to display on seven segment LED display units. Besides ‘c’ codes were written for better understanding of Fourier series analysis and Nodal analysis for resistive circuits.