Durgesh Savale — Product Engineer

I'm building production-ready verification testbenches for silicon — starting with the fundamentals that matter: self-checking benches, FSM design, and waveform debugging. I'm a final-year B.E(Bachelor's Of Engineering) Electronics & Telecommunication student at Savitribai Phule Pune University, completing my degree in August 2026. Over the past year, I've gone from learning Verilog to designing and verifying 8 complete RTL blocks — Half Adder, Full Adder, 4-bit Ripple Carry Adder, multiplexers, D Flip-Flop, counter, and a full UART transmitter with FSM logic. Every project includes a self-checking testbench, waveform verification, and detailed documentation on GitHub — no classroom-only work. What drives my learning is accuracy: I debug at the waveform level, trace signal transitions, understand why tests pass or fail, and structure testbenches for reuse. My UART Transmitter project required FSM design across 4 states (IDLE → START → DATA → STOP) with proper state transitions — that project taught me how testbench clarity saves hours of integration later. Right now, I'm pushing into SystemVerilog, UVM basics, and constrained-random stimulus generation — the tools teams actually use in production verification flows. I'm open to fresher Design Verification Engineer or RTL Design + Verification roles across Pune, Bangalore, and Hyderabad, and I'm available immediately for internships or full-time roles after june 2026. If you're hiring for verification, designing verification flows, or have guidance on UVM frameworks — let's connect. Always eager to learn. Verilog · SystemVerilog · RTL Design · FSM · Testbenches · Functional Coverage · Assertions · Hierarchical Design · Icarus Verilog · EDA Playground · Git · Linux · Waveform Analysis Actively building in public — github.com/Durgesh000-DS — and open to entry-level verification roles. Let's build bug-free silicon together.

Stackforce AI infers this person is a VLSI Design Verification Engineer with a focus on RTL design and verification.

Location: Pune, Maharashtra, India

Experience: 0 mo