Mayank Chaudhary

Product Engineer

Bengaluru, Karnataka, India8 yrs 4 mos experience

Key Highlights

  • Experienced in SystemVerilog and UVM methodologies.
  • Proven track record in design verification roles.
  • Strong background in digital circuit design.
Stackforce AI infers this person is a Design Verification Engineer with expertise in semiconductor and digital design industries.

Contact

mayankc551@gmail.comLinkedIn

Skills

Core Skills

SystemverilogUniversal Verification Methodology (uvm)

Other Skills

VerilogData StructuresCDigital Circuit Design

Experience

8 yrs 4 mos
Total Experience
2 yrs 1 mo
Average Tenure
2 yrs
Current Experience

Qualcomm

Senior Design Verification Lead

Apr 2024 – Present · 2 yrs · Bengaluru, Karnataka, India · On-site

SystemVerilogUniversal Verification Methodology (UVM)Verilog

Amd

GFX DV Enginner

Mar 2022 – Apr 2024 · 2 yrs 1 mo · Bengaluru, Karnataka, India

Intel corporation

SoC Verification Engineer

Jun 2019 – Mar 2022 · 2 yrs 9 mos · Greater Bengaluru Area

Indian institute of technology, kharagpur

Teaching Assistant

Sep 2017 – Mar 2019 · 1 yr 6 mos

Education

Indian Institute of Technology, Kharagpur

Master of Technology - MTech — INSTRUMENTATION AND SIGNAL PROCESSING

Jan 2017 – Jan 2019

Devi Ahilya Vishwavidyalaya, Indore

Bachelor of Engineering - BE — Electronic and Instrumentation

Jan 2013 – Jan 2017

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