Giuliano Sisto

Software Engineer

Leuven, Flemish Region, Belgium8 yrs experience
Highly Stable

Key Highlights

  • Expert in digital IC design and EDA tools.
  • Led projects in advanced CMOS technology and 3D IC integration.
  • PhD holder with extensive research in hardware architecture.
Stackforce AI infers this person is a Semiconductor R&D expert focused on digital IC design and hardware architecture.

Contact

LinkedIn

Skills

Core Skills

EdaDigital Ic DesignComputer Architecture

Other Skills

Physical DesignDTCOSTCOSemiconductors

About

Researcher in digital IC design, facing the challenges of cutting edge CMOS technology nodes and 3D IC integration with hybrid bonding. Working upfront with EDA and technology R&D towards translating new devices, technologies and architectures into reality.

Experience

8 yrs
Total Experience
3 yrs 2 mos
Average Tenure
1 yr 3 mos
Current Experience

Synopsys inc

Sr. Staff R&D Engineer

Mar 2025 – Present · 1 yr 3 mos · Leuven, Flemish Region, Belgium · Hybrid

EDADigital IC DesignPhysical DesignComputer ArchitectureDTCOSTCO

Imec

4 roles

R&D Project Leader

Jul 2024 – Jan 2025 · 6 mos

Hardware Architect

Oct 2023 – Sep 2024 · 11 mos

  • Drive hardware development for the next generation of computing systems for HPC and AI applications
EDAComputer Architecture

Researcher

Promoted

Nov 2021 – Oct 2023 · 1 yr 11 mos

  • Design and System-Technology Co-Optimization for SoC design at advanced nodes
  • 3D integration EDA enablement and system-level PPA benchmarking
  • Digital and Signoff Flow for both 2D and 3D design solutions
EDADigital IC DesignPhysical DesignSemiconductorsDTCO

PHD Student

Nov 2018 – Oct 2021 · 2 yrs 11 mos

Cadence design systems

PHD Student

Oct 2018 – Nov 2021 · 3 yrs 1 mo · Leuven, Belgium

  • Application Engineer training and ramp-up on the latest Cadence tools for all the steps of the digital flow as well as on the latest advanced nodes technologies
  • JDP between Cadence Design Systems and IMEC, aimed at developing innovative solutions for digital IC design and enable the technology of the future.

Huawei technologies

Engineer Internship

Feb 2018 – Aug 2018 · 6 mos · Nice Area, France

  • Architecture design and physical implementation (using commercial EDA tools) of digital filters for All Digital PLLs

Education

Ecole polytechnique de Bruxelles

Doctor of Philosophy - PhD — Integrated Circuit Design

Jan 2018 – Jun 2022

Politecnico di Bari

Master of Science (MSc) — Electronics Engineering

Jan 2016 – Jan 2018

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