Nov 2024 – Feb 2025 · 3 mos

• In my role as a Staff Engineer, I am responsible for driving the comprehensive functional stress validation for the Neural Signal Processor (NSP)/Neural Processing Unit (NPU) across Qualcomm's mobile, XR/VR, Computing, and Automotive platforms.
• Ensuring the successful integration and performance of advanced neural networks accelerated with state-of-the-art Neural Signal Processor.
• I provide technical oversight, optimize validation processes, and collaborate closely with cross-functional teams to achieve robust performance and reliability for Qualcomm's AI-driven solutions.

Nov 2021 – Nov 2024 · 3 yrs

• In my role, I am accountable for conducting comprehensive functional stress validation for the Neural Signal Processor (NSP) and Neural Processing Unit (NPU) incorporated in a wide range of Qualcomm mobile, computing, and automotive devices. This encompasses unit-level testing and end-to-end execution of cutting-edge neural networks, utilizing the latest advancements in Neural Signal Processing technology.

Mar 2020 – Nov 2021 · 1 yr 8 mos

• Responsible for the functional stress validation of NSP(Neural Signal Processor) present in the various mobile/compute/auto devices from the Qualcomm.

Apr 2018 – Mar 2020 · 1 yr 11 mos · bangalore

• In my role at Texas Instruments, I held the responsibility for Pre and Post Silicon validation of various IPs found in control microcontroller chips. These IPs included SPI, LPMs, RESETs, Clocks, PLL Wrapper, Quadrature Module, Dual Clock Comparator, Missing Clock Detectors, NMI, and Watchdog.
• My duties encompassed understanding non-executable specifications, developing comprehensive test plans, coding test cases, and debugging on the Cadence PXP Emulator. This work ran parallel to the design verification team but with distinct objectives.
• I actively contributed to suggesting fixes for RTL design issues and collaborated closely with the Software Driverlib team. Additionally, I facilitated the successful execution of the same code in the Post Silicon environment.
• Furthermore, I worked in coordination with the APPs team to ensure the delivery of high-quality design documentation to customers, ensuring their satisfaction with the final product.

Jun 2015 – Apr 2018 · 2 yrs 10 mos · Noida

• In my role at NXP, I was responsible for the functional and electrical validation of various IPs, including SPI, SAI, eDMA, qDMA, and Hardware Debug Events. These IPs were utilized in different Digital Networking SoCs of the QorIQ series. My responsibilities encompassed developing and executing high-quality test cases for post silicon validation. This work was conducted in a dynamic environment with strong interdependencies, where I also provided support for software development. Additionally, I played a key role in debugging any issues that arose during the validation process, and I offered appropriate workarounds to address these challenges.