Harsimran Singh

Product Engineer

Bengaluru, Karnataka, India13 yrs 8 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

14+ years in VLSI physical design and full-chip implementation.
Expert in timing, power, and area closure across advanced nodes.
Proven leadership in managing cross-functional teams.

Stackforce AI infers this person is a Semiconductor Design Expert with extensive experience in Physical Design and SoC implementation.

Contact

Skills

Core Skills

Physical DesignSoc

Other Skills

System on a Chip (SoC)Physical VerificationStatic Timing AnalysisTiming AnalysisPower AnalysisFloorplanningTalusEncounterCalibrePTSIDRCLVSFormalityCadenceVerilog

About

Results-driven SoC Physical Design Lead with 14+ years of experience in VLSI physical design and full-chip implementation, leading complex SoC programs from RTL handoff through successful silicon tapeout. Expert in driving end-to-end physical design execution, mentoring teams, defining implementation strategies, and achieving timing, power, and area targets across advanced technology nodes. Proven track record of managing cross-functional collaboration between RTL, STA, DFT, PD, and verification teams to deliver high-quality silicon under aggressive schedules. Strong leadership experience in block and full-chip integration, methodology improvement, risk management, and execution planning.

Experience

13 yrs 8 mos

Total Experience

3 yrs 5 mos

Average Tenure

7 yrs 4 mos

Current Experience

Mediatek

3 roles

Senior Staff Engineer

Promoted

Jun 2022 – Present · 4 yrs

Led physical design execution for large-scale SoC programs from floorplan to tapeout.
Defined implementation strategy, schedules, and closure plans across multiple blocks.
Managed and mentored physical design engineers to achieve project milestones.
Owned timing, power, congestion, and area closure at full-chip level.
Coordinated with RTL, STA, DFT, packaging, and verification teams globally.
Drove signoff readiness including STA, IR/EM, DRC/LVS, and ECO convergence.
Enabled successful tapeouts meeting PPA targets and schedule commitments.

System on a Chip (SoC)Physical VerificationPhysical designStatic Timing AnalysisPhysical DesignSoC

Staff Engineer

Jan 2019 – May 2022 · 3 yrs 4 mos

Senior Physical Design Engineer

Jun 2017 – May 2018 · 11 mos · Bengaluru Area, India

Worked as physical design engineer, key role involved netlist to gds sign off , Place & Route, Timing , PV & in addition taken responsiblity as block lead in the team.

Physical designPhysical Design

Amd

Senior Physical Design Engineer

May 2018 – Jan 2019 · 8 mos · Bengaluru Area, India

Worked as Physical Design engineer in CPU core team, complete ownership on signoff of timing/power critical blocks that includes Synthesis , Place & Route , Timing fixes , Physical verification.

Physical DesignSystem on a Chip (SoC)SoC

Blackpepper technologies pvt ltd

Senior Physical Design Engineer

Jun 2015 – Jan 2019 · 3 yrs 7 mos · Bengaluru Area, India

Worked as Senior physical design engineer, with key role involved in completing various project assignment at client location Qualcomm, Mediatek, AMD on different technology node.

Physical DesignPhysical VerificationStatic Timing AnalysisSoC

Qualcomm

Physical Design Engineer

Jun 2015 – Jun 2017 · 2 yrs · Bengaluru Area, India

Worked as physical design engineer , key responsibilities include Physical Design, Timing Analysis, Full Chip Utilization Flow , Library generation,
Custom design for DDR PHYS

Uniquify inc

ASIC Phyiscal Design Engineer

Sep 2010 – Jan 2013 · 2 yrs 4 mos · San Francisco Bay Area - San Jose

Worked onsite in San Jose, USA. Accomplish responsibility for Project Setup, Floor planning, power routing, Timing Driven place and Route, Verification (DRC, LVS, FM, and ANT), RC Extraction and Static Timing Analysis & custom Power.