Harutyun Krrikyan

Software Engineer

Cork, Ireland14 yrs 9 mos experience

Highly Stable

Key Highlights

Expert in ASIC and FPGA digital design.
Proven track record in hardware validation and prototyping.
Strong background in Verilog and USB protocols.

Stackforce AI infers this person is a Semiconductor expert with a focus on digital design and FPGA development.

Contact

krrikyan.harut@yahoo.com LinkedIn

Skills

Core Skills

Digital DesignsVerilog

Other Skills

USB3.2FPGADisplayPortPythonRTL DesignDebuggingField-Programmable Gate Arrays (FPGA)ResearchPERLCWindowsLinuxC (Programming Language)Python (Programming Language)Prototyping

Experience

14 yrs 9 mos

Total Experience

3 yrs 3 mos

Average Tenure

1 yr 9 mos

Current Experience

Synopsys inc

ASIC Design Engineer Sr. Staff

Sep 2024 – Present · 1 yr 9 mos · Dublin, Ireland

Digital Designs

Qualcomm

Staff Engineer

Dec 2020 – Sep 2024 · 3 yrs 9 mos

Digital Designs

Synopsys inc

ASIC Digital Design Engineer Sr. I

Aug 2019 – Nov 2020 · 1 yr 3 mos · Yerevan,Armenia

Developed simple (Verilog based) verification environment for USB3.2.
Developed FPGA prototype for DisplayPort TX controller and have done hardware validation.
Maintenance of DisplayPort TX controller IP (RTL enhancements, CDC, RDC analysis etc.).

Digital DesignsVerilogUSB3.2FPGADisplayPort

Altered silicon, inc.

Digital Design Engineer

Apr 2019 – Aug 2019 · 4 mos · Yerevan,Armenia

Developed FPGA miner software and miner testing environment.
Participated in FPGA miner design:
o development/modification of various hashing algorithms
o ensuring timing closure
o FPGA resource estimation
Developed fee collection server (with Python), worked on software and hardware support for fee collection system.

Digital DesignsFPGAPython

Synopsys inc

3 roles

Supervisor II, ASIC Digital Design

Jan 2019 – Mar 2019 · 2 mos · Yerevan,Armenia

Lead hardware validation and prototype development projects for USB3.0 and DisplayPort controllers.

ASIC Digital Design Engineer

Aug 2012 – Jan 2019 · 6 yrs 5 mos · Yerevan,Armenia

Developed FPGA prototypes for various IPs (DPTX, USB, OHCI, EHCI).
Developed verification environments(Verilog based) for different IPs.
Have led release process of OHCI and EHCI controller IPs (RTL bug fixes, CDC/RDC/Lint analysis, maintenance of verification environment etc.).
Participated in development of DisplayPort TX controller IP.
Supported software engineers to interpret programming model of DisplayPort controller.

Intern

May 2011 – Aug 2012 · 1 yr 3 mos · Yerevan,Armenia

Solutions Group:
Test automation of Odyssey Yield Management System with Perl scripting language.
Educational department:
Participated in development of standard cell library.
Have done Physical/Functional Verification.
Work with DC and ICC.
Developed design automation script with Perl.