Aug 2021 – Jun 2025 · 3 yrs 10 mos · Bengaluru, Karnataka, India · On-site

• Leading STA activities for a 28nm project. Responsible for functional and test mode constraints development, PPA optimization & timing closure.
• Worked on 16nm project. Responsible for functional and test mode constraints development and timing closure
• activities.
• Worked on a very low power design and provided solution for various issues pertaining to low power.
• performed various experiments to lower dynamic/leakage/total power consumption.
• Worked closely with PnR and Synthesis team to address the challenges faced by them.
• Provided solution for CTS build related challenges resulted because of low power design at 16nm/28nm

May 2018 – Aug 2021 · 3 yrs 3 mos · Noida, Uttar Pradesh, India · On-site

• Client NXP Semiconductors Noida
• Worked in STA domain on 40nm,16nm and 5nm technology node.
• Developed Functional mode constraints to perform block-level timing closure on different tech nodes.
• Successfully carried out the interface timing budgeting and ETM generation at block level, which led to smooth chip top STA execution in the signoff stage.
• Worked with Synthesis and the PNR team throughout the design cycle to solve any physical design challenges.
• Dynamic power recovery and Leakage recovery was performed to reduce the power consumption.
• PTECO/MSECO fixes and functional setup/hold fixes were generated for timing closure activity.
• DRV, MPW and gltich analysis was performed to ensure quality timing closure.
• Constraints validation using GCA and check timing analysis was carried out to ensure quality of constraints

May 2017 – Apr 2018 · 11 mos · Austin, Texas Area

• Performing STA on 12nm technology using primetime
• Focus on area reduction and low power implementation
• Performed setup and hold fixes
• Implemented ECOs in innovus

Jun 2016 – Oct 2016 · 4 mos · San Francisco Bay Area

• Working on Xtensa Tensilica IP
• Physical design Team

Oct 2015 – May 2016 · 7 mos · School of Electrical, Computer and Energy Engineering

• RTL design/Verification of parallelized QR decomposition using Givens Rotation for MIMO application:
• Look up table based implementation to minimize the power
• Programming of CEVA dsp in Mindspeed board
• Offload FIR filter operations in frame detection and synchronization block to CEVA

Mar 2011 – Dec 2014 · 3 yrs 9 mos

• Development of Synopsys and Cadence Parasitic Extraction methodologies (28nm, 45nm, 65nm, 130nm):
• Correlation of Lumped capacitance, Coupled Capacitance and resistances between StarRC and QRC.
• Investigation of the capacitance/resistance extraction inaccuracies and determining the root cause.
• Analysis of the issues related to metal fill handling, wire edge enlargement and fringe capacitance.
• Design and automation of improved Parasitic Extraction flow.
• Development of Synopsys and Cadence STA/SI analysis methodologies (28nm, 45nm, 65nm, 130nm):
• Correlation of STA/SI accuracy between ETS/Tempus, Primetime and Spice.
• Investigation of delay differences and analysis of timing paths/stages.
• Analysis of issues in aggressor alignment, clock grouping, electrical filtering and glitch.
• Design of specifications for pessimism reduction and accuracy enhancement solutions for integration into STA/SI tools.
• Design and automation of improved STA/SI signoff flow.
• Deployment of the enhanced tools and flows on five production designs.
• Recognized with the Team Titanium Award for development of STA/SI methodology for DSP & MCU designs.
• Characterization of Noise Libraries:
• Design and automation of Spice based library characterization process for accurate crosstalk analysis using makeCDB.