Jaipal Reddy Nareddy — Senior Software Engineer

17+ Years of experience in software development of EDA and FPGA tools. Effective and collaborative leader with a proven track record of leading high-performing teams to deliver exceptional software solutions. Strong technical background in software development, combined with exceptional leadership and communication skills. Adept in end-to-end development of software products from requirements gathering and analysis to designing, implementation & coding, testing, deployment, and maintenance. Extensive experience in OOD and programming in C, C++, Python, and TCL. Good knowledge of IP-based design and SOC design flows with IP-XACT(IEEE 1685), FPGA design flows, and embedded systems design and software development. Strong analytical skills with proficiency in debugging, and problem-solving. Strong background in runtime performance improvement, parallel programming, multithreading, and resolving the porting issues of C/C++ applications. I hold 5 US patents in FPGA tool flows and have published one paper.

Stackforce AI infers this person is a Software Development Leader in EDA and FPGA industries.

Location: Hyderabad, Telangana, India

Experience: 18 yrs