James Lin — Director of Engineering
* Passionate in tackling the challenges in LC/RO PLL design, high speed clock dividers and clock path jitter optimizations * Building SerDes PLL's in the latest technology nodes
Stackforce AI infers this person is a leader in Analog and Mixed Signal Design within the Semiconductor industry.
Location: Richmond Hill, Ontario, Canada
Experience: 22 yrs 5 mos
Skills
- Analog Circuit Design
- Mixed Signal
Career Highlights
- Expert in LC/RO PLL design and optimization.
- Proven track record in high-speed clock dividers.
- Leadership in Analog and Mixed Signal Design.
Work Experience
Synopsys Inc
Sr Manager, Analog and Mixed Signal Design (3 yrs 4 mos)
Manager II, Analog Design and Mixed Signal Design (5 yrs 6 mos)
Staff Analog Designer (6 yrs 3 mos)
AMD
MTS Analog Designer (4 yrs 6 mos)
Fresco Microchip
Analog Designer (4 yrs 2 mos)
Synopsys
R&D Engineer (2 yrs)
Education
Bachelor of Applied Science (BASc) at University of Waterloo
