Jayakumar Chinnaiyan — Software Engineer
Looking continuously for opportunities to learn and grow as an individual. • Good Knowledge on Physical Design tools like Synopsys ICC & ICC2, DC, PT-SI, Formality, ICV, Cadence Innovus, Voltus & RTL compiler. • Having experience on Floor-planning, Power planning, Place n Route, Fixing timing violations, Power analysis & its solutions, Flow development based on Synopsys RM, Formal equivalence checks, PV implementation. • Understanding of file formats such as LEF, DEF, LIB, SDC, SPEF and SDF. • Familiar with projects in Physical Design at Block level. • Scripting knowledge of TCL & PERL. • Knowledge on concepts of STA, CTS, LVS, RV and DRC.
Stackforce AI infers this person is a VLSI Design Engineer with expertise in Physical Design and Static Timing Analysis.
Location: Villupuram, Tamil Nadu, India
Experience: 12 yrs 3 mos
Skills
- Physical Design
- Static Timing Analysis
Career Highlights
- Expert in Physical Design tools and methodologies.
- Strong background in Static Timing Analysis and Power Planning.
- Proficient in scripting with TCL and PERL.
Work Experience
AMD
Member of Technical Staff (3 yrs 10 mos)
Sankalp Semiconductor
Senior Technical Lead (2 yrs 10 mos)
Lead Engineer (5 yrs 7 mos)
Wipro Limited
Senior Project Engineer (2 yrs 2 mos)
Project Engineer (2 yrs 2 mos)
Education
Bachelor of Engineering - BE at Anna University Chennai
Bachelor's degree at Panimalar Engineering College
