J

John Jekel

CEO

Waterloo, Ontario, Canada7 mos experience

Key Highlights

  • Passionate about ASIC industry and low-level software.
  • Developed multiple RISC-V CPU implementations.
  • Interned at top tech companies like Apple and Synopsys.
Stackforce AI infers this person is a highly skilled ASIC and FPGA engineer with a focus on low-level software development.

Contact

Skills

Core Skills

FpgaSystemverilogC/c++LpddrAsicMicroarchitectureSecurityVerificationSoftware Development

Other Skills

TCLPerlAssembly LanguageLZ4Research SkillsHigher Education ResearchElectronics Hardware DesignFirmwareChiselPython (Programming Language)DesignOptimizationData ModelingLinux System AdministrationGit

About

I am a fourth-year Computer Engineering student at the University of Waterloo on my last academic term. I'm super passionate about the ASIC industry, low-level software, and computers in general! I love working on low-level hardware and software projects! I have lots of experience with SystemVerilog, C/C++, and designing and building up circuits! Most recent project: "irve", a Linux-capable RISC-V CPU emulator! https://github.com/angry-goose-initiative/irve And its sister project: "LETC", a Linux-capable RISC-V hardware implementation! https://github.com/angry-goose-initiative/letc Another fun one: "JZJCoreF", a 2-stage pipelined RISC-V CPU implementation! https://gitlab.com/JZJisawesome/jzjcoref

Experience

7 mos
Total Experience
7 mos
Average Tenure
--
Current Experience

Apple

CPU Microarchitect / RTL Engineer

Jan 2026Present · 5 mos · Austin, Texas, United States · On-site

  • Begins June 2026

Altera

IP RTL Design Engineering Internship

Sep 2025Dec 2025 · 3 mos · Toronto, Ontario, Canada · On-site

  • Used SystemRDL to implement registers for a new Ethernet AN/LT IP, targeting an upcoming Altera FPGA.
  • Actively investigating and developing AXI and Avalon arbiters, decoders, and bridges for use in the IP.
  • This internship is still ongoing, so there's more to come as the term progresses.
SystemVerilogTCLPerlFPGA

Synopsys inc

Firmware Engineering Intern

Jan 2025Apr 2025 · 3 mos · Ottawa, Ontario, Canada · On-site

  • Wrote an optimized LPDDR DQ bus read-write training sequence for a next-generation Synopsys PHY.
  • Implemented an in-place LZ4 compression library, requiring only a small, fixed amount of auxilary memory.
  • Enabled reproducible firmware builds for a customer by identifying non-determinism in the C compiler itself.
  • Improved runtime of several training steps by 20% though code optimization and analysis of ARC assembly.
LPDDRC/C++Assembly LanguageLZ4

University of waterloo

Undergraduate Research Assistant - Configurable NoC Architecture

May 2024Dec 2024 · 7 mos · Waterloo, Ontario, Canada · On-site

  • Implemented credit-based flow control in a Butterfly Fat Tree Network-on-Chip (BFT NoC) topology in Verilog. Targeted the AMD UltraScale+ FPGA family, working under the guidance of Dr. Nachiket Kapre during 3A and 3B academic terms. Became basis for a couple of research projects and used to teach ECE 720.
  • Created tools to verify correctness and extract timing, area, and power data from logs for comparative analysis.
SystemVerilogResearch SkillsHigher Education ResearchFPGAASIC

Untether ai

RTL Design / Firmware Intern

Jan 2024Apr 2024 · 3 mos · Toronto, Ontario, Canada · On-site

  • Designed an AXI width conversion IP from scratch in SystemVerilog for the main datapath of a future ASIC. Handles out-of-order AXI 4 traffic at multiple TB/s in aggregate without introducing bubbles.
  • Created a synthesizable AXI-to-SRAM subordinate from scratch to aid in FPGA prototyping and simulation of AXI managers in Untether IP.
  • Brought up a PCIe subsystem (PHY, controller, and datapath logic). Identified and overcame silicon bugs, and wrote firmware sequences in C to stress the link and send data bidirectionally.
  • Identified and fixed memory corruption in diagnostic firmware using AddressSanitizer and Valgrind.
SystemVerilogElectronics Hardware DesignFirmwareC/C++ASICFPGA+1

University of waterloo

Undergraduate Research Assistant - Hardware Platform Security

Sep 2023Dec 2023 · 3 mos · Waterloo, Ontario, Canada · Remote

  • Implemented Blinded Memory (BliMe) and taint-tracking into the Gemmini hardware accelerator, using Chisel, under the guidance of Hossam ElAtali and Dr. N. Asokan during 2B academic term.
  • Resulting paper "Data-Oblivious ML Accelerators using Hardware Security Extensions” accepted into IEEE HOST 2024: https://ieeexplore.ieee.org/document/10545398
Research SkillsHigher Education ResearchFPGASecurityChisel

Marvell technology

ASIC Design & Verification Engineering Intern

May 2023Aug 2023 · 3 mos · Ottawa, Ontario · Hybrid

  • Developed UVM testcases to verify a future ASIC targeting an advanced 5 nm process.
  • Identified more than 5 RTL bugs and their causes, wrote fixes, and made recommendations with Jira.
  • Created a Python script to parse SystemVerilog modules and automatically generate assertions (SVAs).
  • Recommended IP solutions to the chip lead, communicated directly with vendors and internal teams, and performed comparative analysis between IP options.
VerificationSystemVerilogPython (Programming Language)

Huawei technologies canada co., ltd.

2 roles

ASIC Design Intern

Sep 2022Dec 2022 · 3 mos · Ottawa, Ontario, Canada (Remote) · Remote

  • Designed a major block in SystemVerilog for a future networking ASIC targeting an advanced 7 nm process.
  • Optimized the packet processing pipeline to detect “halt” instructions and clock-gate flops in downstream stages to reduce power usage by up to 10%.
  • Wrote VLIW assembly test stimulus to debug and ensure the functional correctness of the design.
  • Analyzed the timing, area, and power impacts using SpyGlass, and documented findings formally.
DesignSystemVerilogASICMicroarchitecture

CPU Performance Engineer

Jan 2022Apr 2022 · 3 mos · Ottawa, Ontario, Canada (Remote)

  • Developed micro-architectural aspects of a C++ cycle-approximate model for AArch64 (ARM 64-bit) cores.
  • Profiled the model to identify opportunities for optimization with Valgrind and KCacheGrind.
  • Rewrote C/C++ standard library functions using x86 AVX intrinsics, reduced heap allocations, and
  • tweaked data structures to improve model runtime performance by 21.12x.
  • Modelled data with Python, taking performance statistics from SQLite databases to automatically generate webpages leveraging JavaScript and Apache ECharts.
Software DevelopmentOptimizationData ModelingC/C++Microarchitecture

Redberry restaurants

Team Member

Jun 2021Aug 2021 · 2 mos · Leamington, Ontario · On-site

  • Accepted payment from customers, produced orders as
  • requested, and cleaned surfaces and machinery.

Cardinal carter secondary school

Math Tutor

Oct 2019Jan 2020 · 3 mos · Leamington, Ontario, Canada

Education

University of Waterloo

Bachelor of Applied Science - BASc — Computer Engineering

Sep 2021May 2026

Cardinal Carter Catholic Secondary School

High School Diploma — High School

Jan 2017Jan 2021

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