John Jekel — CEO
I am a fourth-year Computer Engineering student at the University of Waterloo on my last academic term. I'm super passionate about the ASIC industry, low-level software, and computers in general! I love working on low-level hardware and software projects! I have lots of experience with SystemVerilog, C/C++, and designing and building up circuits! Most recent project: "irve", a Linux-capable RISC-V CPU emulator! https://github.com/angry-goose-initiative/irve And its sister project: "LETC", a Linux-capable RISC-V hardware implementation! https://github.com/angry-goose-initiative/letc Another fun one: "JZJCoreF", a 2-stage pipelined RISC-V CPU implementation! https://gitlab.com/JZJisawesome/jzjcoref
Stackforce AI infers this person is a highly skilled ASIC and FPGA engineer with a focus on low-level software development.
Location: Waterloo, Ontario, Canada
Experience: 7 mos
Skills
- Fpga
- Systemverilog
- C/c++
- Lpddr
- Asic
- Microarchitecture
- Security
- Verification
- Software Development
Career Highlights
- Passionate about ASIC industry and low-level software.
- Developed multiple RISC-V CPU implementations.
- Interned at top tech companies like Apple and Synopsys.
Work Experience
Apple
CPU Microarchitect / RTL Engineer (5 mos)
Altera
IP RTL Design Engineering Internship (3 mos)
Synopsys Inc
Firmware Engineering Intern (3 mos)
University of Waterloo
Undergraduate Research Assistant - Configurable NoC Architecture (7 mos)
Untether AI
RTL Design / Firmware Intern (3 mos)
University of Waterloo
Undergraduate Research Assistant - Hardware Platform Security (3 mos)
Marvell Technology
ASIC Design & Verification Engineering Intern (3 mos)
Huawei Technologies Canada Co., Ltd.
ASIC Design Intern (3 mos)
CPU Performance Engineer (3 mos)
Redberry Restaurants
Team Member (2 mos)
Cardinal Carter Secondary School
Math Tutor (3 mos)
Education
Bachelor of Applied Science - BASc at University of Waterloo
High School Diploma at Cardinal Carter Catholic Secondary School