K

Karthikeyan V

Software Engineer

Bengaluru, Karnataka, India7 yrs 8 mos experience
Most Likely To Switch

Key Highlights

  • Expert in ASIC digital design and RTL integration.
  • Proficient in high-speed interface design and verification.
  • Experienced in VLSI design across multiple technology nodes.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in ASIC and FPGA development.

Contact

LinkedIn

Skills

Core Skills

Asic Digital DesignRtl DesignNoc DesignPcie IntegrationVlsi DesignRisc V IntegrationSoftware Defined RadioFpga Development

Other Skills

RTL IntegrationPerlPCIeSystemVerilogVerdiField-Programmable Gate Arrays (FPGA)Xilinx ISEMemory compilersUFS SubsystemSDCRTL SimulationDigital DesignsIP developmentStatic Timing Analysislibero

About

ASIC Frontend Design #RTL #LINT #CDC #RDC #UPF #Synthesis #constraints Knowledge with Memory Compilers. Support for DV/DFT Closure. Knowledge on Synthesis, & Timing Contraints. Analyzing Timing Paths & power across the subsystem. worked on various nodes[SA-2nm/TSMC-3nm,4nm,5nm,7nm/UMC-28nm/GF-22nm]

Experience

7 yrs 8 mos
Total Experience
1 yr 11 mos
Average Tenure
2 yrs 3 mos
Current Experience

Synopsys inc

ASIC Digital Design - Staff Engineer

Mar 2024 – Present · 2 yrs 3 mos · Bengaluru · On-site

  • UFS 3.0 Subsystem/ PCIe Gen6 Subsystem
RTL IntegrationRTL DesignASIC Digital Design

Microchip technology inc.

Senior Engineer I Design

Oct 2022 – Mar 2024 · 1 yr 5 mos · Hyderabad, Telangana, India · On-site

  • NoC with DDR & PCIe for Polarfire FPGA's
PerlPCIeNoC DesignPCIe Integration

L&t technology services limited

Senior Engineer - VLSI

Mar 2022 – Oct 2022 · 7 mos · Chennai, Tamil Nadu, India & Mysore Karnataka India · On-site

  • RISC V Integration
SystemVerilogVerdiVLSI DesignRISC V Integration

Data patterns (india) pvt ltd

Engineer

Oct 2018 – Mar 2022 · 3 yrs 5 mos · Chennai, Tamil Nadu, India · On-site

  • Software Defined Radio(SDR)
  • IO Module in Precision Approach Radar(PAR)
Field-Programmable Gate Arrays (FPGA)Xilinx ISESoftware Defined RadioFPGA Development

Education

Mepco Schlenk Engineering College

Bachelor of Engineering - BE — Electrical and Electronics Engineering

Jan 2014 – Jan 2018

Sri Aurobindo Mira Mat.Hr.Sec.School

12th Grade — Computer Science

Jun 2013 – Mar 2014

Sri Aurobindo Mira Mat.Hr.Sec.School

10th Grade

Jun 2011 – Mar 2012

Stackforce found 100+ more professionals with Asic Digital Design & Rtl Design

Explore similar profiles based on matching skills and experience

Senthil Kumar Murugaiah

Senthil Kumar Murugaiah

Sr. Manager Silicon Design Engineering

at AMD

Hyderabad, India25 yrs 8 mos exp
Product ManagementEngineering Management
Sushil Sirsat

Sushil Sirsat

Research Scholar

at Visvesvaraya National Institute of Technology

India12 yrs 7 mos exp
Analog Integrated Circuit DesignSignal Integrity
ABHINANDAN .

ABHINANDAN .

Analog Design Engineer (External)

at Synopsys Inc

Una, India2 yrs exp
Analog Circuit Design
Sreekanth Billupati

Sreekanth Billupati

Digital Design Engineer

at C2i Semiconductors

Sri Potti Sriramulu Nellore, India6 yrs 11 mos exp
Product Design5G New Radio (NR)Team Leadership
Varun Kumar

Varun Kumar

Synthesis/STA Engineer (Contractor)

at AMD

Hyderabad, India1 yr 1 mo exp
Integrated Circuit DesignPhysical Design
Basannagouda Reddy

Basannagouda Reddy

Director R&D

at Synopsys Inc

San Francisco, United States23 yrs 2 mos exp
Neeraj Parmar

Neeraj Parmar

Intern

at AMD

Indore, India5 mos exp
Field-Programmable Gate Arrays (FPGA)
Vijayalaxmi Raddiyavar

Vijayalaxmi Raddiyavar

SRAM library validation

at Intel

Bengaluru, India4 yrs 6 mos exp
SRAMLibrary ValidationComponent DesignPDK ValidationSimulation