Kavya Narendla — Software Engineer
Having knowledge on Logic Design and Physical design procedures. Working experience on projects in ICC2 tool & CADENCE GENUS & INNOVUS tool.Basic Knowledge of RTL Coding in Verilog language & knowledge on TCL scripting. Done various projects from Synthesis to PNR flow including floor Planning,Placement,CTS, Routing & Eco flow.good knowledge in STA and Timing fixing by PRIME TIME tool.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Physical Design and Timing Analysis.
Location: Hyderabad, Telangana, India
Experience: 6 yrs 6 mos
Skills
- Physical Design
- Static Timing Analysis
Career Highlights
- Expert in Physical Design and Static Timing Analysis.
- Proficient in multiple EDA tools including ICC2 and Cadence.
- Strong foundation in RTL coding and TCL scripting.
Work Experience
AMD
Silicon Design Engineer 2 (3 yrs 3 mos)
Siliconus Technologies Pvt Ltd
Physical Design Engineer (3 yrs 3 mos)
Education
Bachelor of Technology at Rajiv Gandhi University of Knowledge Technologies, RKValley (RAC)
Puc at Rajiv Gandhi University of Knowledge Technologies, RKValley (RAC)
