Dec 2022 – May 2025 · 2 yrs 5 mos

• Design 1:
• Customer:                  Lattice semiconductor
• Type of design:          WRIO (High performance IO)
• Team size:                  12
• Voltage domain:        1.2 V / 1.5 V / 1.8 V / 2.5 V / 3.3 V
• Termination:               Single ended/differential/Duo-differential (SSTL/HSTL/LVDS)
• Driver Strength:         Ranging from 2 mA up to 24 mA
• Including full DDR support.
• Design 2:
• Customer:                   Lattice semiconductor
• Type of design:          HPIO (High performance IO)
• Team size:                  18
• Voltage domain:        2.5v, 1.8v, 1.2v
• Termination:               Single ended/differential/Duo-differential
• Single ended & Differential ended driver list involved SSTL, HSTL, LVDS, with sub-LVDS, SLVS, and MIPI.
• SSTL Driver with weak CTLE could facilitate high-bandwidth connectivity for LPDDR4/DDR4 and DDR5 with data rates up to 2400 Mbps.
• 100 Ω dynamic differential input termination and programmable single-ended termination (40/50/60/75 Ω).
• MIPI with data rate up to 7.98 Gbps for camera and display applications.
• Major blocks of design comprised CTLE with drivers & equalizers including PLL & delay cells.

Oct 2019 – Nov 2020 · 1 yr 1 mo

• Sony (SSS) Image sensor group 12nm/22nm
• Type of design: Image sensor (MIPI)
• Subsystem: C-phy, D-Phy, M-phy
• Technology node: 12 nm
• Voltage domain: 1.8v, 1.2v, 800mv
• Termination: 50 Ω & 100 Ω
• Driver: SSTL & LVDS
• Timeline: Oct 2019 to May 2020

Jun 2018 – Sep 2019 · 1 yr 3 mos

• Analog design/Analog Mixed signal
• HSIO ,SERDES ,High speed links

Feb 2018 – Jan 2026 · 7 yrs 11 mos

Feb 2018 – Jun 2018 · 4 mos

• Analog design/Analog mixed signal 112gbps

Jun 2017 – Jan 2018 · 7 mos · Bengaluru Area, India · Hybrid

• HSIO 48 Gbps with Technology node of 7 nm/14nm & speed reaching 48 Gbps.
• We worked on the qualification of critical PHY blocks like Equalizers (CTLE/DFE), CDR, PLL (resistor-DCO). Challenges: Rx margin feasible with 24-inch path was 40mv, and we need to let
• This margin to be 20mv, we were supposed to check changes in DFE with CTLE block and Sampler at 7nm FINFET

Jul 2016 – Dec 2016 · 5 mos · Bengaluru Area, India · On-site

• Analog Circuit design ( SERDES ) with Team building, Team management & Design sign off
• Analog circuit design & enhancement, Characterization .lib generation, Serializer with de-serializer circuit, TX/RX circuits, ODT, output driver, differential high speed input receivers, Calibration schemes, slew rate control.Schmitt trigger, Level-shifters, Drivers, Noise correction, Bias-gens, PLL with CDR .

Dec 2011 – Dec 2012 · 1 yr · Bengaluru Area, India

• I/O design with migration and characterization.
• Responsible to design full custom blocks (SERDES -Transmitter & receiver with termination block). High-speed transceiver logic- family of controlled impedance design pads includes single-ended and differential drivers and receivers, along with compensation circuitry for process, voltage, and temperature (PVT) variations.

Mar 2006 – Nov 2011 · 5 yrs 8 mos · Noida

• Responsible to design full custom blocks (SERDES -Transmitter & receiver with termination block). High-speed transceiver logic- family of controlled impedance design pads includes single-ended and differential drivers and receivers, along with compensation circuitry for process, voltage, and temperature (PVT) variations.
• Team was supposed to be always in hurry to be well perfect in I/O Design High speed interface design with RAMs ,ROM & Standard cell with Front-end conversion to back-end in process.
• Involved Micro-architectural definition, Circuit specification, Schematic entry, Simulation and Characterization, layout design, physical, functional, timing and power verifications, design checks, design reviews and documentation.

Oct 2002 – Dec 2005 · 3 yrs 2 mos · Noida · On-site

• was part of "Development & release of" MIMAGIC8 processor
• Responsible to be the part of Analog design/Analog & MS team for SERDES design for CPU communication.