KOTIKE SIDDARTHA

Operations Associate

Kozhikode, Kerala, India1 yr 8 mos experience

Key Highlights

Passionate about VLSI and Integrated Circuit Design.
Optimized FPGA architectures for high-speed applications.
Strong academic performance with a 9.84 GPA.

Stackforce AI infers this person is a VLSI Design specialist with a focus on FPGA architectures and digital electronics.

Contact

Skills

Core Skills

Digital Vlsi DesignFpga Architectures

Other Skills

Digital ElectronicsFPGA prototypingStatic Timing AnalysisXilinx VivadoDigital IC DesignHLSVerilog HDLVery-Large-Scale Integration (VLSI)Data StructuresObject-Oriented Programming (OOP)LTSpicePython (Programming Language)Leadership

About

Hey, I am Siddartha, Passionate about VLSI and Integrated Circuit Design, I find joy in continuous learning and exploring new technologies. With a friendly and approachable nature, I enjoy collaborating with others and sharing knowledge. Outside of work, I love playing badminton and am always eager to discover new experiences and opportunities in the ever-evolving tech world.

Experience

1 yr 8 mos

Total Experience

1 yr 8 mos

Average Tenure

1 yr 8 mos

Current Experience

Iit bhubaneswar

Summer Research Intern

May 2025 – Jul 2025 · 2 mos

Research Area: Digital VLSI Architecture Design; FPGA Architectures
Guidance: Dr. Ayan Palchaudhuri, Assistant professor, School of Electrical and Computer Sciences, IIT Bhubaneswar
Title: High Performance VLSI Architecture Design of Leading Zero Counters with Resource-Aware FPGA Mapping
The key contributions of the project are as follows:
Optimized FPGA architectures for high-speed Leading Zero Counters (LZCs) on Xilinx Kintex-7
(xc7k160tfbg484-1), leveraging fast carry chains and MUXF7 primitives to achieve significant critical path reduction and improve resource utilization.
Leveraged RLOC-based placement to tightly co-pack logic within slices, enabling improved timing closure and demonstrating fine-grained floorplanning.
A modular construction approach is adopted, enabling seamless extension to wider datapaths using structurally consistent logic across stages.
Evaluation of 8 to 128 bit configurations demonstrates substantial delay reductions
48% speedup for 8-bit LZC (1.556 ns → 0.807 ns).
31.5% , 16.3%, 19.9% faster implementation for 32- and 64-bit variants,
while maintaining competitive area and power efficiency compared to state-of-the-art LUT-based implementations.