Apr 2021 – Present · 5 yrs 2 mos

• Working in RTL design team for Video and Image enhancement cluster of Intel Graphics while building scalable infrastructure. Responsibilities include feature feasibility analysis, logic complexity, effort estimation, micro-architecture design implementation.
• Conceived micro-architectural changes and executed RTL implementation for multiple pivotal features for various design blocks of Media Graphics team. Designed and validated multi-million Gate Count (GC) design.
• Worked on various algorithmic pipeline blocks used in Dolby Vision and HDR workloads.
• Managed unit-level validation and throughput testing for multiple design units, overseeing the creation of unit test plans, test content generation, and management of functional coverage.

Apr 2019 – Mar 2021 · 1 yr 11 mos

• Contributed as an RTL designer and validator on a sophisticated media unit focused on image scaling. Engaged closely with the architecture teams to grasp top-level specifications, framing microarchitecture, and implemented RTL design support for the cluster.
• Conceptualized and implemented micro-architectural enhancements.
• Contributed to test plan initialization, debugging of test scenarios, bug reporting, coverage management, regression management, and Engineering Change Orders (ECOs) for design blocks.
• Collaborated and supported multiple stakeholders like Integration team for front-end flow lint, spyglass clean-up, connectivity reviews; Validation/Verification teams for pipe level related debugs, coverage reviews, etc. and Synthesis/Backend team for throughput alignment, timing, LoL and gate count closures.

Aug 2017 – Mar 2019 · 1 yr 7 mos