Manoj Kallu — Product Engineer

I am a Computer Engineering graduate student at Texas A&M University with 3+ years of industry experience in RTL and digital design for high-performance FPGA and SoC systems. Before starting my MS, I worked as an RTL Design Engineer at Mavenir, contributing to 5G radio platforms built on Xilinx RFSoC devices. My work involved designing and integrating datapaths, packet-processing modules, and multi-clock domain logic for high-speed Ethernet and O-RAN systems. I worked across the RTL development cycle including micro-architecture design, RTL implementation, STA, CDC analysis, timing closure, and FPGA validation. Previously at C-DAC, I developed RTL for IEEE 802.15.4 PHY/MAC layers, implementing modulation and demodulation pipelines and validating FPGA communication systems. Technical strengths • Verilog / SystemVerilog / VHDL • RTL micro-architecture and digital design • AXI, Ethernet, and high-speed interfaces • Static Timing Analysis (STA) and CDC • FPGA and ASIC design flows (Synopsys, Cadence, Xilinx) I am currently seeking Summer 2026 internships in: • RTL Design • Digital / ASIC Design • FPGA / SoC Design I’m especially interested in roles involving high-performance silicon, SoC architecture, and hardware acceleration. Feel free to connect if you work in RTL, ASIC, or digital design.

Stackforce AI infers this person is a skilled RTL and FPGA design engineer with experience in telecommunications and high-performance computing.

Location: College Station, Texas, United States

Experience: 4 yrs 4 mos