Mohd Arfeen — Software Engineer
I am a Design Verification Engineer. Skill Set: HDLs : Verilog HVL : System Verilog Methodologies : UVM Programming Languages : C EDA Tool : Modelsim (Questa),Xilinx ISE Design Operating Systems : Linux, Windows Protocols : AMBA – AXI 3.0,APB 3.0,UART,SPI,I2C Scripting : Perl Qualities: Being an active person with participating, volunteering, Coordinating. Being a confident person and to handle multiple task simultaneously. Mohd Arfeen
Stackforce AI infers this person is a VLSI Design Verification Engineer with expertise in semiconductor technologies.
Location: Delhi, India
Experience: 5 yrs 11 mos
Skills
- System Verilog
- Uvm
- Vlsi Design
Career Highlights
- Experienced in SoC design verification.
- Proficient in Verilog and System Verilog.
- Hands-on experience with FPGA design.
Work Experience
HCLTech
Design Verification Engineer (4 yrs 7 mos)
Truechip
Verification Engineer (1 yr 4 mos)
C-DAC Mohali
Internship Trainee (1 mo)
Education
Bachelor of Engineering at CHANDIGARH UNIVERSITY
