Muneet _

Project Manager

Gurgaon, Haryana, India8 yrs 9 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in RTL design and digital video protocols.
Proven experience in high-speed protocols like PCIe/CXL.
Strong leadership in managing complex engineering projects.

Stackforce AI infers this person is a Digital Video Protocols and RTL Design expert with strong engineering capabilities.

Contact

Skills

Core Skills

Rtl DesignProtocol DevelopmentVhdlWeb Development

Other Skills

Timing ClosureOn Board TestingRTL Code DevelopmentDisplay Port Receiver Module DevelopmentARINC818 Video Processing and Switching Module DevelopmentXilinx GTX WrapperPlanningRequirement CaptureMEAN StackXilinx VivadoLogic SynthesisEngineeringEmbedded SystemsMicrosoft WordMicrosoft Office

About

RTL developer with experience of working on Digital Video Protocols as well as High Speed Protocols PCIe/CXL Gen-X. Developed RTL code following DO-254 Level B Process.

Experience

8 yrs 9 mos

Total Experience

4 yrs 4 mos

Average Tenure

8 yrs 3 mos

Current Experience

Logic fruit technologies

3 roles

Project Lead RTL Design

Promoted

Apr 2022 – Present · 4 yrs 2 mos

Protocol DevelopmentRTL Design

Module Lead - RTL Design

Jul 2020 – May 2022 · 1 yr 10 mos

R&D Engineer RTL Design

Mar 2018 – Jul 2020 · 2 yrs 4 mos

Developed RTL code to implement FPGA-based digital designs, working from specification through to system integration following DO-254 Level B Lifecycle(Planning till the Detailed Design).
> Planning, Requirement Capture, Detailed Design Data Documentation.
> RTL Code in VHDL.
> Xilinx GTX wrapper for the Design.
> Timing Closure and On Board Testing.
Development of Display Port Receiver Module for ARINC818 Video Processing and Switching Module(AVPSM).
> Xilinx GTX Wrapper.
> RTL Code for AUX Interface for Communication with Standard Display Port Source.
> Integration with AVPSM.
> On Board Testing.
Development of ARINC818 Video Processing and Switching Module(AVPSM)
> Planning and Requirement Capture,
> Timing Closure,
> On Board Testing,
> Linting Report using HDL Designer.

VHDLTiming ClosureOn Board TestingRTL Code DevelopmentDisplay Port Receiver Module DevelopmentARINC818 Video Processing and Switching Module Development+1