Apr 2021 – Jan 2023 · 1 yr 9 mos

• Responsible for recommending products at the SKU level instead of Product level.
• Delivered 5% ATC rate lift.

Jan 2020 – Apr 2021 · 1 yr 3 mos · Houston, Texas, United States

Feb 2014 – Jan 2020 · 5 yrs 11 mos · Greater Houston

• Developed and deployed end to end products:
• Physical modelling using regression techniques
• Online surveillance monitoring system using classification techniques
• Equipment failures prediction
• Reinforcement Learning for closed loop control

May 2012 – Aug 2012 · 3 mos

•  Investigated the structure of a practical DSP CPU which includes:
• A Harvard CPU architecture.
• A fast booth multiplexer.
• Array handling: Indirect addressing, circular/modulo addressing, bit reversed addressing.
•  Transferred the DSP CPU, which was originally designed in gate level VHDL, to an RTL level Verilog design. The design includes nearly 10,000 gates with almost 200 ports and 700 registers. The RTL design in Verilog helps to drastically speed up the modification process of the chip as well as well accommodates the verification process, which is normally implemented using System Verilog.

May 2010 – Dec 2013 · 3 yrs 7 mos

• UH Wireless networking, Signal processing and security Lab, Houston, TX
• Research Assistant
•  Location Based Service (LBS) for wireless device:
• Developed a stochastic model to handle missing data. The aim is to detect revisited locations as well as new locations using WiFi received signal strengths as the signatures. The approach is highly energy efficient, determining the places in a quickest way. User locations information is highly desired in scheduling users’ access, network resource management, and D2D communications.
• Developed a Dynamic Hidden Markov Model, which evolves itself in accordance with users’ movements. The states (or places) of the hidden Markov model are determined dynamically and updated in an unsupervised manner.
• Developed a method to predict the next visiting location using Deep Learning. User movement trajectories are fed into Deep Learning to learn about the moving patterns. Once the moving patterns can be extracted, the next location can be predicted precisely.
•  Wireless security: Developed an unsupervised approach to detect Masquerade and Sybil attacks using device fingerprinting. Device dependent features are extracted and assigned to the devices. Using nonparametric Bayesian approach, the number of devices can be found and compared with the number of registered devices to detect an attack.
•  Data mining and processing: Experimental data were used for all the projects. Data processing techniques include finding hidden causes, latent variable, classification with unknown number of classes, Bayesian inference, Deep Network inference.

Jan 2007 – Dec 2008 · 1 yr 11 mos

• Designed an I2C interface on FPGA. The project includes an I2C slave sending data over I2C bus to an I2C master. The I2C master, controlled by MicroBlaze, will then send data via RS232 port on a Spartan 3E board to a host computer. On the host computer, a C# program is used to display received data in the form of waveform.
• Designed a pipeline (MIPS) 32-bit processor on FPGA which is capable of handling various structural, data, control and branch hazards.
• Designed a RISC 32-bit processor on FPGA.
• Designed and laid out a 32-bit Accumulator using TSMC 0.25um process: The accumulator includes a 32-bit full-adder and a 32-bit register.
• Designed an ultra low supply voltage, 8-bit, 200ksamples/s Successive Approximation ADC using a capacitor-based DAC and a passive Sample and Hold in TSMC 0.25um process.