Nandini S

Software Engineer

Hyderabad, Telangana, India8 yrs 6 mos experience

Key Highlights

8 years of experience in design verification.
Expert in architecting verification environments.
Proven track record in achieving high coverage.

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in advanced IP and SoC components.

Contact

Skills

Core Skills

GpgpuGraphics Processing UnitSystemverilogUniversal Verification Methodology (uvm)

Other Skills

OpenCLSynopsys toolsVCSDebuggingNCSimQuestaSimAnalytical SkillsC (Programming Language)CommunicationProblem SolvingCode CoverageAMBA AHBAMBA AXIVerilog

About

Senior Design Verification Engineer with 8 years of experience verifying advanced IP and SoC components . Skilled in architecting and optimizing verification environments using SystemVerilog (SV) and UVM, I specialize in PHY calibrations, power management, DFI interfaces, and industry-standard protocols including PCIe, GDDR, MIPI, AMBA, and SPI. I have a proven track record of developing robust verification plans, debugging complex RTL issues, and achieving high functional and code coverage. I bring strong problem-solving skills, leadership qualities, and mentoring experience to drive high-quality design sign-offs and product success. Passionate about delivering reliable verification solutions and fostering collaboration within teams.

Experience

8 yrs 6 mos

Total Experience

1 yr 10 mos

Average Tenure

11 mos

Current Experience

Qualcomm

Senior Lead Engineer

Jul 2025 – Present · 11 mos · Hyderabad, Telangana, India · On-site

GPU verification

GPGPUGraphics Processing Unit

Amd

Senior Silicon Design Engineer

May 2022 – Feb 2025 · 2 yrs 9 mos · Bengaluru, Karnataka, India · Hybrid

Spearheaded GDDR PHY verification, ensuring compliance with specifications and enhancing design integrity.
Developed and refined a constraint random verification environment using SystemVerilog and UVM, improving efficiency.
Collaborated closely with design engineers to identify and debug regression failures, leading to functionally correct design blocks.

SystemVerilogUniversal Verification Methodology (UVM)

Intel corporation

Pre-Si Validation engineer - Grade 5

Jun 2021 – May 2022 · 11 mos · Hybrid

Developed and maintained a comprehensive weekly regression testing schedule, ensuring timely updates to the testing dashboard.
Collaborated closely with the design team to identify, track, and resolve bugs, enhancing overall product quality.
Debugged and resolved test failures, ensuring a seamless testing process and high-quality outcomes.