Naveenkumar GS — Product Engineer
ASIC Digital Design Engineer specializing in RTL Design and ISO 26262 Functional Safety for PCIe and Ethernet IPs. Skilled in Verilog/SystemVerilog, SVA, UVM, FPGA prototyping, AMBA protocols, and digital design fundamentals. Experienced in RTL development, implementation of safety logic blocks, and development of safety work products including FMEDA, DFA, and Safety Case. Proficient in VCS, QuestaSim, SpyGlass, Design Compiler, and Jama.
Stackforce AI infers this person is a Digital Design Engineer specializing in ASIC and Functional Safety.
Location: Tamil Nadu, India
Experience: 7 mos
Skills
- Rtl Design
- Verification
Career Highlights
- Expert in RTL Design and Functional Safety.
- Proficient in Verilog/SystemVerilog and UVM.
- Experienced in safety logic block implementation.
Work Experience
Synopsys Inc
ASIC Digital Design Engineer (Contractor) (7 mos)
Functional Safety Intern (1 yr 1 mo)
Maven Silicon
RTL Design And Verification Engineer (1 yr 1 mo)
Education
Bachelor's degree at PSG College of Technology
