Dec 2019 – Jun 2021 · 1 yr 6 mos · Greater Hyderabad Area

Jan 2019 – Dec 2019 · 11 mos · Noida, Uttar Pradesh, India

• Quicksave-Restore
• Designed and implemented a feature 'Quicksave-Restore' to restore the designs.
• It's highly used in the fault application where design to be tested via different fault modes.

Apr 2018 – Sep 2018 · 5 mos · Noida, Uttar Pradesh, India

• Fault Injection App
• Designed and implemented a fault injection app for establishing the fault tolerance of the design.
• This help in taking the system into a fault-tolerant state in case of failure.

Jul 2017 – Feb 2018 · 7 mos · Noida, Uttar Pradesh, India

• Rtl-Trigger
• Designed and Implemented RTL-Trigger a Debugging tool to improve DUT testing.
• Liaised with multiple development teams to understand and manage interdependencies among different products and flow integration issues for cross-development projects for the product.

Jun 2016 – Dec 2016 · 6 mos · Noida, Uttar Pradesh, India

• Implemented an open source tool Libvirt for managing platform virtualization, which manages KVM, VMware, QEMU and other virtualization technologies.

Dec 2015 – Jan 2016 · 1 mo · Noida sector 126,India

• I was selected as a Internship programme, As a Intern in Mentor Graphics.
• I had the opportunity to work on C++, perl, STL and perl Interfacing for the "Axcomp Software" which include various Architectural unit such as :-
• 1.The software architecture of axcomp is concerned with how users of the Axcelo FPGA prototyping solution will use the system to setup and run their design efficiently
• 2.The purpose of the Axcomp Software will be distributing and managing tasks that can be run in parallel with the Desktop based design.
• 3.‘Axcomp’ is a PC based design that will allow the customers to run Axcelo FPGA prototyping
• solution. It is a comprehensive solution for the users to manage and schedule their executions.
• Design Engineer can configure their designs to be run through the flop
• using two customizable Configuration files. These configuration files will act as the base of entire design execution.

Dec 2014 – Jan 2015 · 1 mo · Greater Delhi Area

• Designed a Time controlled charging adapter in RL-78 microcontroller family and Selected as a best student in Renesas Electronics PVT. LTD.

Jun 2014 – Jul 2014 · 1 mo · Noida, Uttar Pradesh, India

• Learned VLSI Design using Verilog and implemented an 8-bit Processor and UART serial communication protocol.

Apr 2014 – Apr 2015 · 1 yr · Delhi

• UGV-DTU is a team of undergraduate students who are working towards creating an autonomous vehicle capable of traversing a course whilst avoiding obstacles to reach its destination.