Pallavi Das

Software Engineer

Bengaluru, Karnataka, India12 yrs 8 mos experience

Highly Stable

Key Highlights

Expert in RTL to GDSII flow with Synopsys tools.
Strong background in Physical Design and Timing Closure.
Proficient in Analog and Mixed Signal Design methodologies.

Stackforce AI infers this person is a VLSI Design Engineer with expertise in Physical Design and Analog/Mixed Signal methodologies.

Contact

Skills

Core Skills

Physical DesignTiming ClosureAnalog And Mixed Signal DesignFunctional Verification

Other Skills

RTL to GDSII flowMCMM and MV flowsSynopsys backend tool IC Compiler-IIphysical implementationsynthesisformal equivalenceplacementoptimizationlow power checksCTSroutingcrosstalk delay/noise analysisReal Value Modeling (RVM)VerilogBehavioral model development

About

Career Objective: Good understanding various stages of IC Design flow starting from the RTL level to the Signoff stage, with hands-on experience in different Synopsys EDA tools like Design Compiler, IC Compiler-II and DFT Compiler. ================================================================= Skills:- Physical Design(Placement, CTS, Routing) Static Timing Analysis Synthesis Behavioral Modeling VLSI Design ==================================================================== Synopsys -Design Compiler ICC-2 Prime time Cadence Virtuoso and Spectra LT Spice MATLAB

Experience

12 yrs 8 mos

Total Experience

3 yrs

Average Tenure

1 yr 7 mos

Current Experience

Samsung semiconductor

Senior Staff Engineer

Nov 2024 – Present · 1 yr 7 mos · Bangalore Urban, Karnataka, India · Hybrid

Intel corporation

SOC Design Engineer

Jul 2018 – Oct 2024 · 6 yrs 3 mos · Bengaluru, Karnataka, India

Synopsys inc

2 roles

Physical Design Engineer

Promoted

Aug 2016 – Jul 2018 · 1 yr 11 mos

Associate CAE

Oct 2015 – Aug 2016 · 10 mos

Good understanding of RTL to GDSII flow
Familiar with different flows and methodologies (MCMM and MV flows)
Expertise in Synopsys backend tool IC Compiler-II
Focused mainly on physical implementation & timing closure flow with synthesis, formal equivalence,placement, optimization, low power checks, CTS , routing, crosstalk delay/noise analysis etc using Synopsys tools
Compared and analysed various matrices like timing, area, memory, runtime for different release of DC-ICC2(16.03) and worked to improve customer productivity.
Working on timing aspect of physical design to get optimise WNS(worst negative slack) in designs.
Working on generating NDM (New Data Model) i.e Library generation for ICC-II

RTL to GDSII flowMCMM and MV flowsSynopsys backend tool IC Compiler-IIphysical implementationtiming closuresynthesis+9

Stmicroelectronics

Graduate Engineering Trainee

Jul 2014 – Jul 2015 · 1 yr · Delhi NCR

Development of Real Value Modeling (RVM) methodology to incorporate true analog behavior of AMS IPs in Verilog through WREAL modeling technique. The technique has been successfully used in modeling PLL analog loop behavior in Verilog.
Behavioral model development of PLLs, voltage regulators in Verilog
Worked on Deployment of equivalence checking methodology for clock generation, Thermal Sensor.
Front end designing and verification of Analog and Mixed signal IPs
Test bench Creation
Test plan and Test vector coding
Power Aware simulations
Functional and Timing Simulations
Functional Coverage
RTL Design
ASIC Design