Daivik Reddy Bhaskar — Product Engineer

I'm passionate about full RTL-to-GDSII chip implementation and timing closure in advanced nodes. At ChipEdge Technolgies, I've executed end-to-end physical design on three tapeout-ready SoC projects working in 14nm FinFET and 28nm CMOS technologies. 𝗛𝗶𝗴𝗵𝗹𝗶𝗴𝗵𝘁𝘀: • Closed timing with WNS < 0.05ns across all three designs (Falcon, JBI, ChipTop) • Reduced dynamic power by 15–20% through targeted power gating • Achieved DRC/LVS-clean signoff with 80%+ area utilization on every design • Hands-on with the full PD flow: synthesis, floorplanning, power planning, placement, CTS, routing, STA, signoff 𝗧𝗼𝗼𝗹𝘀: Synopsys Design Compiler, IC Compiler II (ICC2), PrimeTime, StarRC, IC Validator (ICV); Cadence Virtuoso (Layout XL, PVS) 𝗦𝗸𝗶𝗹𝗹𝘀: RTL-to-GDSII, Static Timing Analysis (STA), Place & Route, Clock Tree Synthesis, Power Planning, DRC/LVS Signoff, TCL Scripting 𝗦𝗲𝗲𝗸𝗶𝗻𝗴: Spring 2027 / Summer 2027 Physical Design internships or co-ops. Open to connecting with PD engineers, hiring managers, and recruiters. Feel free to message me directly.

Stackforce AI infers this person is a Semiconductor Physical Design Engineer with expertise in RTL-to-GDSII flows.

Experience: 0 mo