Paras Bhanwal

Software Engineer

Hyderabad, Telangana, India3 yrs 7 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in high-complexity IP and SoC-level emulation builds.
Proficient in ZeBu and Palladium platforms for FPGA products.
Significant reduction in debugging time through innovative frameworks.

Stackforce AI infers this person is a Semiconductor Emulation and Prototyping Engineer with expertise in IP validation and testing.

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Skills

Core Skills

Ip DevelopmentSilicon ValidationEmulation/prototypingTest Automation

Other Skills

CXLPCIeFPGAPalladiumZebuTransactor IntegrationEmulationPrototypingVibe CodingClinePlatform DevelopmentTest Automation FrameworksRouting ProtocolsEmerging TechnologiesDebugging

About

Silicon Design & Verification Engineer with specialization in Emulation and FPGA Prototyping. My expertise lies in delivering high-complexity IP and SoC-level emulation builds using ZeBu and Palladium platforms for AMD’s next-generation FPGA products. My responsibility includes :- ~ RTL to emulation platform development ~ Transactor integration and testing ~ IP/SoC level testbench development ~ Waveform capture and RTL debugs ~ Post-silicon bring-up support ~ RTL development for RTL feature testing. ~ Simulation bring-ups using VCS ~ Custom FPGA prototyping setups for IP level designs Technical Highlights: Emulation/Prototyping: ZeBu, Palladium, and FPGA prototyping builds. Protocols: PCIe, CXS, AXI, and APB. Design & Verification: RTL development, SystemVerilog, transactor integration. Tools & Scripting: VCS, Verdi, Vivado, Python, TCL, and C.

Experience

3 yrs 7 mos

Total Experience

1 yr 9 mos

Average Tenure

3 yrs 3 mos

Current Experience

Amd

2 roles

Senior Silicon Design Engineer

Apr 2025 – Present · 1 yr 1 mo · On-site

Developed CXL monitor IP for capturing CXL traffic in PL, verified and tested this IP on FPGA at 300Mhz, IP used by multiple validation teams for RTL debugs.
Developed PCIe streaming IP for validating PCIe features, verified and tested this IP at 100MHz.
Used Cline to reduce soft IP development time by 20%.

CXLPCIeIP DevelopmentSilicon Validation

System Design Engineer

Jan 2023 – Mar 2025 · 2 yrs 2 mos · On-site

Responsible for Palladium platform development, transactor integration, testing and execution for multiple IP/SoC level projects.
Development and execution of functional coverage and performance testing.
Developed a generic protocol analyzer framework for palladium platform, resulting in 30% reduction in debugging time.
Planning and implementation of emulation and prototyping builds for IP/SoC level designs to minimize the platform differences, minimal platform induced issues and easy RTL bug reproduction.
Created emulation equivalent simulation environment for ZEBU platform to ensure platform reliability.
Improved emulation execution scripts to make them more user-friendly and enhance resource efficiency resulting in precise debugs and smaller wavedumps.
Collaborated with validation teams on optimizing emulation processes and RTL debugs.
Custom FPGA prototyping platforms for IP level designs.
Involved in post-silicon platform bring-ups and debugs.

PalladiumZebuEmulation/PrototypingTest Automation

Terascale

Design Engineer

Aug 2022 – Dec 2022 · 4 mos · Hyderabad, Telangana, India · On-site

Conducted sanity tests for palladium platforms to ensure reliability.
Designed automation framework for reset testing on Palladium and Protium platforms.

PalladiumTest AutomationSilicon Validation