Parmjot Singh

Product Manager

Bengaluru, Karnataka, India20 yrs 1 mo experience

Highly Stable

Key Highlights

17+ years of VLSI industry experience
Expertise in Netlist to GDSII flow
Managed 25+ tapeouts successfully

Stackforce AI infers this person is a VLSI Physical Design expert with extensive experience in Analog custom layout and chip design.

Contact

Skills

Core Skills

Chip Level FloorplanningPower PlanningAnalog Custom Layout

Other Skills

CTS & Timing closure using ICC2/Fusion CompilerRC ExtractionVirtuoso for Custom AMS layoutCalibre for Physical verificationEngineering ManagementRedhawk for EM/IR

About

With overall VLSI industry experience of 17+ years, possesses expertise in Netlist to GDSII flow with current focus on chip level floor planning, power planning, critical signal planning, congestion analysis, EM/IR analysis & signoff using Redhawk & physical verification along with managing physical design team in Microchip India design center. Possesses experience in Analog custom layout as a lead. Handled 25+ tapeouts which includes A0 revisions & metal revisions. Looking forward to enhancing my skill set through working in the area of Analog custom layout, Physical design & EMIR effects on cutting edge technologies.

Experience

20 yrs 1 mo

Total Experience

5 yrs 4 mos

Average Tenure

4 yrs

Current Experience

Microchip technology inc.

4 roles

Physical Design Manager

Jun 2022 – Present · 4 yrs · Bengaluru, Karnataka, India · On-site

Managing physical design team of current size 4 at India design center, with responsibilities
including project planning, resource allocation, schedule tracking, mentoring & coordinating cross
site tasks among team members. Involved in resource projection, interview process & managing on-boarding process for new hires. Writing focal feedback, development planning & conducting regular 1-on-1 meetings with the team.

Chip level floorplanningpower planningCTS & Timing closure using ICC2/Fusion CompilerRC Extraction

Principal Engineer - Physical Design

Promoted

Jan 2016 – Nov 2021 · 5 yrs 10 mos

Working experience in Physical design team for 16-bit Micro-controller with job responsibilities including Floor-planning, die area estimation, Pad ring to meet different package requirements, power grid creation & congestion analysis, CTS & Timing closure. Sensitive signal routing, RC extraction & optimization for analog/power routes to meet required constraints. IR & EM analysis using Redhawk,
Chip level Physical verification using Calibre & sign-off checks

Chip level floorplanningpower planningCTS & Timing closure using ICC2/Fusion CompilerRC Extraction

Senior Engineer II, Analog Custom Layout

Jun 2015 – Dec 2016 · 1 yr 6 mos

Custom Layout team lead, responsibilities include such as supervising, delegating, and empowerment of team, writing focal review & conducting one on one meeting with the team members. Successfully lead layout team for streamout of two test shuttles from IDC along with various full chip tapeout which includes around three A0 & six metal revisions.

Senior Engineer I, Analog Custom Layout

Aug 2010 – Jun 2015 · 4 yrs 10 mos

As an individual contributor, accomplished successful tapeout of around thirteen full chips, out of
which eight are released to production, one testshuttle of tsmc90nm & completion of various analog
macros such as LDO, ADC, DAC, Regulator supervisor, Oscillator etc for various technologies such
as TSMC 180nm, 90nm, 40nm & SFC70. Full chip responsibility includes supporting physical design team for LVS/DRC feedback, prune generation & review, providing overlay cells, PCF, final streamout database preparation & review of fractured database from the foundry.

RC ExtractionVirtuoso for Custom AMS layoutAnalog custom layout

Intel corporation

SOC Design Engineer

Nov 2021 – Jun 2022 · 7 mos · Bengaluru, Karnataka, India · On-site

Worked on Power, Performance, Area (PPA) activities on 14nm & 10nm Intel process nodes with
focus on optimizing process technology by aiding decisions on metal stack selection, device
optimization & cell architecture with data gathered from fully routed, timing-optimized layouts of
various blocks. Tool, Flow, Methodology (TFM) improvements, which can help improve the best achievable Quality of Results (QoR) for a given process options.

Wipro

Sr Project Engineer, Analog Custom Layout

Jun 2010 – Aug 2010 · 2 mos · Bengaluru, Karnataka, India · On-site

Kpit cummins infosystems limited

Senior Member Technical Staff

Mar 2006 – Jun 2010 · 4 yrs 3 mos · Bengaluru, Karnataka, India · On-site

Onsite support for Dialog semiconductor, UK on AMS verification & later for analog custom layout
blocks such as bandgap, opamp, PLL, charge pump, DAC etc. Involved in various on-site & off-site projects which include RTL implementation of memory wrapper for Hitachi as offshore project support, memory compiler implementation for ST Micro (Noida) as on-site support.

Virtuoso for Custom AMS layoutCalibre for Physical verificationAnalog custom layout