Pavan Kumar Kaipa

CTO

Bengaluru, Karnataka, India28 yrs 7 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Led multi-site teams of 350+ in SOC design.
Transformed design productivity and quality metrics.
Expert in AI and High Performance Computing architectures.

Stackforce AI infers this person is a leader in Semiconductor design with expertise in AI and High Performance Computing.

Contact

Skills

Core Skills

Silicon DesignAsicSoc DesignAiMixed Signal Ip DesignAnalog DesignCircuit DesignIc Design

Other Skills

DatacenterAI AcceleratorsGPUsDesign MethodologyPhysical DesignAnalog SimulationMixed Signal VerificationParasitic RC-ExtractionPower EstimationDesign LayoutCharacterizationSemiconductorsVerilogEDAVLSI

About

Accomplished leader with ~27 years experience in the following areas: Directing SOC Products Design in AI, High Performance Computing, MCU, GFX SOC space and Mixed Signal IP Design (SerDes, DDR, Chip to Chip Connectivity IO, HBM, GPIOs...), Design Methodologies and Automation. Led large multi-site teams of size ~350 for designing industry-leading SOC Products in Automotive, Consumer - GPU /High Performance Computing on advanced process technologies and advanced packaging 2.5D/3D . Experienced in building highly performing/innovative teams around the globe including USA, India, Malaysia, Israel. Led multiple transformations - Including technically driving big leaps in Design Productivity/Quality/KPIs, leading Cultural Transformations, building organizations for scale and grooming multiple leaders.

Experience

28 yrs 7 mos

Total Experience

7 yrs 1 mo

Average Tenure

20 yrs 6 mos

Current Experience

Intel corporation

4 roles

Head of Silicon Engineering - Intel Foundry Services, India

Aug 2021 – Present · 4 yrs 10 mos

Drive Custom ASIC /Turnkey products from Architecture to Productization in the space of AI, Datacenter and High-end Clients. Leading a diverse Engineering talent (300+) in the space of Silicon Design, IP Design, FW, Post Si.

Silicon DesignASICAIDatacenter

Sr. Director - SOC Engineering, High Performance Computing

Promoted

Mar 2020 – Aug 2024 · 4 yrs 5 mos

Sr. Director for Front-to-Back Design of SOCs in High Performance Compute Domain (AI Accelerators, GPUs).
Organizational and Business Strategy Development

SOC DesignAI AcceleratorsGPUsAI

Director of Engineering and Principal Engineer

Promoted

Dec 2005 – Mar 2020 · 14 yrs 3 mos

Held multiple Engineering positions including SOC Design Lead, Mixed Signal IP Design Lead and Design Methodology Lead, Design Flows Lead and Foundational IP Design lead. Held global positions for IP Design Methodology as a Technologist, Global Place and Route team leader and Horizontal SOC Design Team Lead. Grew from a Senor Design Engineer's role to Global Director role for Certain functions in the organization.
1. Delivered Front-to-back Design of 2 GPU based SOCs and Physical Design For multiple GPU IPs
2. Led 200+ppl Global Team Physical Design of SOCs, IP Subsystems, Mixed Signal IPs (PCIe Gen*, DDR, On Package IOs).
2. Design Manager for High Speed IO Design (SerDes, Die2Die connectivity, DDR,...etc).
3. Driving End-to-End Design Methodologies/SOCIntegration for Intel's Mixed Signal IP Development
4. Definition of IP Compiler (Automation) Strategy for GPIO, Voltage Regulators and SRAMs
5. Foundational IP (Standard Cells and SRAMs) for multiple technology nodes

Mixed Signal IP DesignDesign MethodologyPhysical DesignSOC Design

Technical Leader/Engineering Manager

Apr 2000 – Jul 2004 · 4 yrs 3 mos

Responsible for leading accurate parasitic RC-Extraction, IR Drop, Crosstalk Analysis and Power Estimation flows

Parasitic RC-ExtractionPower EstimationCircuit Design

Infineon technologies

Analog CAD and Mixed Signal Verification Manager

Jul 2004 – Dec 2005 · 1 yr 5 mos

Responsible for managing a 16 people team developing design flows for Analog & Mixed Signal Simulation, RF Simulation and Chip/Package Co-design. Pavan was also responsible for driving University relations.

Analog SimulationMixed Signal VerificationAnalog Design

Philips semiconductors

Sr. IC Design Engineer

Nov 1997 – Apr 2000 · 2 yrs 5 mos

Pavan was responsible for Design, Layout, Characterization and EDA view development for Standard Cells and General Purpose I/Os on Philips 0.35U, 0.25U, 0.18U Technologies

Design LayoutCharacterizationIC Design