Pavan Kumar R

Software Engineer

Bengaluru, Karnataka, India13 yrs experience

Highly Stable

Key Highlights

Extensive experience in formal verification and functional ECO.
Proficient in multiple VLSI design tools and methodologies.
Strong background in low-power design and ASIC development.

Stackforce AI infers this person is a VLSI Design Engineer with expertise in formal verification and ASIC development.

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Skills

Core Skills

Formal VerificationFunctional Eco

Other Skills

Conformal LECQADebuggingHDL-VerilogTClPERLTesting tools : Encounter Test (Cadence)Atalanta.Functional verification tools : Model-SimNC-SimConformal (Cadence)QuartusProgramming Languages : Basics of C.Layout tools : Virtuoso (Cadence).ASIC

Experience

13 yrs

Total Experience

2 yrs 2 mos

Average Tenure

2 yrs 1 mo

Current Experience

Intel corporation

Senior Physical Design Engineer

Apr 2024 – Present · 2 yrs 1 mo · On-site

Qualcomm

Staff Design Engineer/Manager

Jul 2018 – Mar 2024 · 5 yrs 8 mos · On-site

Cadence design systems

Lead Application Engineer

Nov 2016 – Jun 2018 · 1 yr 7 mos · Bengaluru Area, India

Intel corporation

Design Engineer

Jul 2014 – Oct 2016 · 2 yrs 3 mos · Bengaluru Area, India

Infineon technologies

PVP IP Engineer

Apr 2014 – Jul 2014 · 3 mos · Bengaluru Area, India

Developing, maintenance and support of Physical Verification Run sets for all the Infineon Technology Nodes.
Areas of Responsibility:
Developing PERC Run sets, maintenance and support of IFX products.
ESD and other reliability checks development, automation and bug fixing of older run sets.

Accenture services private limited

Software Engineer

Aug 2013 – Mar 2014 · 7 mos · India,Bangalore

Worked on Perl automation and Microsoft web development

Intel corporation

Post Graduate Technical intern at INTEL

Aug 2012 – Jun 2013 · 10 mos · Banglore

1. working in the SoC Design Automation team on Formal Equivalence Checking(including PA-FEV) and Functional ECO’s.
2. Enhanced and performed QA on FEV and ECO flows (Control wrapper around the tool).
3. De-bugged various SoC’s at block and partition level to pass FEV (and PA-FEV) and worked
on functional ECO implementations.
4. Addressed the tool limitations while using UPF in Conformal-LP (In specific PA-FEV).
Project: “POWER AWARE FORMAL EQUIVALENCE CHECKING & ECO CHALLENGES
[METHODOLOGY /LIMITATIONS] FOR IP’s AND SoC’s”.