Pinnu Sharan Kumar

Software Engineer

Andhra Pradesh, India4 yrs experience

Key Highlights

Expert in ASIC design verification and FPGA testing.
Led a team for successful BT SoC verification.
Published research on DMA controller in 2021.

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in ASIC and FPGA technologies.

Contact

Skills

Core Skills

Functional VerificationSystemverilogSoc VerificationIp Level VerificationVery-large-scale Integration (vlsi)

Other Skills

Code CoverageCoverage IssuesField-Programmable Gate Arrays (FPGA)Gate Level SimulationGroup DiscussionsLean Process ImprovementManagementShell ScriptingTeachingUniversal Verification Methodology (UVM)FPGAUVMGLS simulationsTiming analysisScript Coverage

About

HDL: Verilog HVL: System Verilog Methodology: UVM Tools worked on: Mentor graphics (Questasim), Synopsys(VCS), Cadence (Xcelium) Standard Bus protocols: AMBA APB, AMBA AHB High speed Bus protocols: SDIO Speciaities: Test bench development, Test plan from scratch, TB bring up of FPGA, ASIC for SoC verification and ASIC GLS. Publication: Paper on DMA controller in springer 2021. Passion: VLSI passionate to learn new and emerging technologies and looking forward to work on the same.

Experience

4 yrs

Total Experience

2 yrs 3 mos

Average Tenure

1 yr 9 mos

Current Experience

Micron technology

ASIC Design Verification Engineer

Sep 2024 – Present · 1 yr 9 mos · Bengaluru, Karnataka, India · On-site

Code CoverageCoverage IssuesFunctional VerificationSystemVerilogIP level verification

Ignitarium

2 roles

Senior Design Verification Engineer

Promoted

Nov 2023 – Jul 2024 · 8 mos · India · On-site

1. FPGA verification of BT SoC.
2. Coded the new C tests for the FPGA verification.
3. ASIC TB bringup for the BT SoC and the new C tests and UVM tests coded at the SoC level and bug reporting.
4. GLS TB bringup for the ASIC BT SoC.
5. GLS simulations and X propagations issues are reported in the system. Timing paths are checked for violations.
6. Led the DV team of 5 people for the BT SoC verification.
7. Block level and SoC level debugging for the identification of critical functional issues and flaws in the digital design.
8. Scripts are developed for the post processing of the timing violations in the GLS simulations.

Code CoverageCoverage IssuesField-Programmable Gate Arrays (FPGA)Functional VerificationGate Level SimulationGroup Discussions+7

Design Verification Engineer

Apr 2022 – Nov 2023 · 1 yr 7 mos · India · On-site

1. Hands on experience in IP level verification of peripherals SPI, UART, DMA
2. Hands on experience in SoC verification of SDIO foe WiFi chipset.
3. Codes the C tests and UVM tests for SoC verification.
4. Functional coverage models are implemented for the same.
5. Ran the GLS simulations and identified the X propagations and timing anayalis in the system.
6. Codes the Pinmux tests at the SoC level for checking the proper connection of pins and reported the bugs.
7. Debugging of functional failure tests and bug reporting.
8. FPGA verification bring up of BT SoC

IP level verificationSoC VerificationField-Programmable Gate Arrays (FPGA)Gate Level SimulationFunctional VerificationCode Coverage+5

Testbook edu solutions private limited

2 roles

Freelance Writer

Oct 2020 – Mar 2022 · 1 yr 5 mos

Content writing, Solution writing and question creation for various competitive exams like ESE, GATE and other exams related to ECE

Teaching Assistant

Jul 2020 – Oct 2020 · 3 mos

Started Teacher Training Program from July 13 and it is very good for learning new things in quick time.

Ibm

Intern

Oct 2020 – Jun 2021 · 8 mos · Remote

Worked on Design and Development of DMA controller for openpower processor of IBM. Testcase running with regression depending on the customized commands.
Worked on the tool Xilinx Vivado till the generation of bitstream.

DMAICVery-Large-Scale Integration (VLSI)

Bharat electronics

Project Trainee

Jan 2018 – Apr 2018 · 3 mos · Machilipatnam, Andhra Pradesh, India

This organization unit is mainly working for Defense and their requirements.
I got opportunity to do my B.tech project with the PSU. My project was FPGA BASED MOTOR CONTROL SYSTEM, where controlling of motor is done with the help of coding which is done in HDL language and that is checked with the help of FPGA. This motor is used to control the lens and other different applications in defense.

Central electronics limited

Summer Intern

Jun 2017 – Jul 2017 · 1 mo · New Delhi, Delhi, India

This organization is working for many departments like Solar Photovoltaic, Railway Electronics, Microwave electronics, Electronic Ceramics, Cathoderay Protection etc...
I had a some part of experience with their work that is related to PIEZO ELECTRIC GENERATOR.
Construction, working and applications of this.
It was a good experience during internship with the company employees.