Prabhat Yadav — Software Engineer

- ASIC Digital Design Engineer with 2+ years of experience in microarchitecture and RTL design. Specialized in AXI/APB protocol design and HBM3/4 memory controller development, with hands-on expertise in timing closure on advanced TSMC nodes. - Experienced in end-to-end RTL quality flows including Lint, CDC/RDC, synthesis, and STA using Synopsys tools. Proven track record of improving performance, optimizing latency, and delivering high-quality, timing-closed designs. - Passionate about solving complex design challenges, high-speed interfaces, and scalable memory architectures. -Design understanding of HBM3/4 DRAM Memory Architecture -Different HBM memory densities,On-chip error detection/correction mechanisms using verilog - Worked on different ASIC Front-end design/Verification genAI tools bring up & validation for different IPs. -Worked in Design & Creation of Packages for RMMI, MIPI M-PHY IP -HDL(Verilog & System Verilog), STA & Digital Electronics knowledge. •Shell/Perl Scripting Experience: •Worked on High -Level Synthesis using C++(catapult), Debugging RTL, Estimation of QoRs, Analysis of different suites in Regression, Makefile, Creation of Testcases for replication of Customer's Issues, Pre & Post Synthesis. •Trained in Design Verification using System Verilog (Semi-Design). Previous Experience : - ETL Developer , SQL developer, worked as Linux Admin,Worked in Shell India pvt.ltd IT Centre.

Stackforce AI infers this person is a Semiconductor and Telecommunications expert with strong RTL design and memory architecture skills.

Location: Hyderabad, Telangana, India

Experience: 6 yrs 8 mos